MAX3107EAG+T Maxim Integrated Products, MAX3107EAG+T Datasheet - Page 44

• Manufacturer Part Number: MAX3107EAG+T
• Description: IC UART SPI/I2C 128 FIFO 24SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107EAG+T

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MAX3107EAG+T; MAX3107EAG+TTR

Figure 15. SPI Single-Cycle Read
Figure 16. SPI Single-Cycle Write
SPI/I
and Internal Oscillator
The MAX3107 can be controlled through SPI or I
defined by the logic on I2C/SPI. See the Pin Configurations
for further details.
The SPI supports both single-cycle and burst-read/write
access. The SPI master must generate clock and data
signals in SPI MODE0 (i.e., with clock polarity CPOL = 0
and clock phase CPHA = 0).
Figure 15 shows a single-cycle read and Figure 16
shows a single-cycle write.
Burst access allows writing and reading in one block by
only defining the initial register address in the SPI com-
mand byte. Multiple characters can be loaded into the
transmit FIFO by using the THR (0x00) as the initial burst
read address. Similarly, multiple characters can be read
out of the receiver FIFO by using the RHR (0x00) as the
SPI’s burst read address. If the SPI burst address is dif-
ferent to 0x00, the MAX3107 automatically increments
44
_____________________________________________________________________________________
SCLK
SCLK
SDO
SDI
SDI
CS
CS
2
A_ = REGISTER ADDRESS
D_ = 8-BIT REGISTER CONTENTS
A_ = REGISTER ADDRESS
D_ = 8-BIT REGISTER CONTENTS
C UART with 128-Word FIFOs
Serial Controller Interface
W
R
A6
A6
A5
A5
SPI Single-Cycle Access
A4
A4
SPI Burst Access
SPI Interface
A3
A3
A2
A2
2
A1
A1
C as
A0
A0
the register address after each SPI data byte. Efficient
programming of multiple consecutive registers is thus
possible. Chip select, CS/A0, must be kept low during
the whole cycle. The SCLK/SCL clock continues clocking
throughout the burst access cycle. The burst cycle ends
when the SPI master pulls CS/A0 high.
For example, writing 128 bytes into the TxFIFO can be
achieved by a burst write access through the following
sequence:
• Pull CS/A0 low
• Send SPI write command
• Send 128 byes
• Release CS/A0
This takes a total of (1 + 128) x 8 clock cycles.
The MAX3107 contains an I
data communication with a host processor (SCL and
SDA). The interface supports a clock frequency up to
400kHz. SCL and SDA require pullup resistors that are
connected to a positive supply.
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
2
C-compatible interface for
D1
D1
D0
D0
I
2
C Interface