ISD15102FYI Nuvoton Technology Corporation of America, ISD15102FYI Datasheet - Page 9

• Manufacturer Part Number: ISD15102FYI
• Description: IC VOICE REC/PLAY 3V 2MIN 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD15100r

Specifications of ISD15102FYI

• Interface: I²S, Serial
• Duration: 2 Min
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• For Use With: ISD-ES15100_USB - BOARD EVALUATION USB FOR I15100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Filter Pass Band: -

Number
Pin
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Pin Name
SPK+
V
SPK-
V
NC
NC
NC
INTB
RDY/BSYB
RESET
NC
NC
GPIO3
GPIO2
GPIO1
V
V
XTALOUT
XTALIN
SSD
CCD
CCD
CCD
_PWM
_PWM
I/O
I/O
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
Function
PWM driver positive output. This SPK+ output, together with SPK- pin,
provide a differential output to drive 8 speaker or buzzer. During
power down this pin is in tri-state.
Or, can be configured as BTL which, together with SPK- pin, provide a
differential voltage output.
Or, can independently switch to AUDOUT or AUXOUT.
Digital Ground for the PWM Driver.
PWM driver negative output. This SPK- output, together with SPK+
pin, provides a differential output to drive 8 speaker or buzzer.
During power down this pin is tri-state.
Or, can be configured as BTL which, together with SPK+ pin, provide a
differential voltage output.
Or, can independently switch to AUDOUT or AUXOUT.
Digital Power for the PWM Driver.
This pin should be left unconnected.
This pin should be left unconnected.
This pin should be left unconnected.
Active low interrupt request pin. This pin is an open-drain output.
An output pin to report the status of data transfer on the SPI interface.
“High” indicates that ISD15100 is ready to accept new SPI commands
or data.
Applying power to this pin will reset the chip. (A high pulse of 50ms or
more will reset the chip.)
This pin should be left unconnected.
This pin should be left unconnected.
GPIO
GPIO
GPIO
Digital power supply pin.
Digital power supply pin.
Crystal interface output pin.
The CLK_CFG register determines one of the following three
configurations: (1) A crystal or resonator connected between the
XTALOUT and XTALIN pins. (2) A resistor connected to GND as a
reference current to the internal oscillator and left the XTALOUT
unconnected. (3) An external clock input to the device and left the
XTALOUT unconnected.
- 9 -
Publication Release Date: July 1, 2010
ISD15100 SERIES
Revision 1.0