ISD5116SY Nuvoton Technology Corporation of America, ISD5116SY Datasheet - Page 26

• Manufacturer Part Number: ISD5116SY
• Description: IC VOICE REC/PLAY 8-16MN 28-SOIC
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISD5100r

Specifications of ISD5116SY

• Interface: I²C
• Filter Pass Band: 1.7 ~ 3.4kHz
• Duration: 8 ~ 16 Min
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (0.300", 7.50mm Width)
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To set up the chip for Memo Record, the configuration registers are set up as follows:
Only those portions necessary for this mode are powered up.
This mode sets the chip up for local playback of messages recorded earlier. The playback path is from
the MULTILEVEL STORAGE ARRAY to the FILTER MUX, then to the LOW PASS FILTER stage.
From there, the audio path goes through the SUM2 SUMMING amplifier to the VOLUME MUX,
through the VOLUME CONTROL then to the SPEAKER output stage. We will assume that we are
driving a piezo speaker element. This audio was previously recorded at 8 kHz. All unnecessary stages
will be powered down.
4. Select the SUM1 SUMMING amplifier path through the FILTER MUX—Bit FLS0 controls the
5. Power up the LOW PASS FILTER — Bit FLPD controls the power up state of the LOW PASS
6. Select the 5.3 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
7. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier — Bits S2M0 and
1. Select the MULTILEVEL STORAGE ARRAY path through the FILTER MUX — Bit FLS0, the
2. Power up the LOW PASS FILTER — Bit FLPD controls the power up state of the LOW PASS
3. Select the 8.0 kHz sample rate—Bits FLD0 and FLD1 select the Low Pass filter setting and
4. Select the LOW PASS FILTER input (only) to the S2 SUMMING amplifier —Bits S2M0 and
CFG0=0010 0100 0010 0001 (hex 2421).
CFG1=0000 0001 0100 1000 (hex 0148).
state of the FILTER MUX. This is bit D4 of CFG1 and it must be set to ZERO to select the
SUM1 SUMMING amplifier path.
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 5.3 kHz sample rate, D2 must be set to ZERO and D3 set to ONE.
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to
select the LOW PASS FILTER (only) path.
6.3.10 Memo and Call Playback
state of the FILTER MUX. This is bit D4 of CFG1 and must be set to ONE to select the
MULTILEVEL STORAGE ARRAY.
FILTER stage. This is bit D1 of CFG1 and it must be set to ZERO to power up the LOW PASS
FILTER STAGE.
sample rate to be used during record and playback. These are bits D2 and D3 of CFG1. To
enable the 8.0 kHz sample rate, D2 and D3 must be set to ZERO.
S2M1 control the state of the SUM2 SUMMING amplifier. These are bits D5 and D6
respectively of CFG1 and they should be set to the state where D5 is ZERO and D6 is ONE to
select the LOW PASS FILTER (only) path.
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Publication Release Date: Oct 31, 2008
ISD5100 SERIES
Revision 1.42