LM4936MH/NOPB National Semiconductor, LM4936MH/NOPB Datasheet - Page 24

• Manufacturer Part Number: LM4936MH/NOPB
• Description: IC AMP AUDIO PWR 2.2W AB 28TSSOP
• Manufacturer: National Semiconductor
• Series: Boomer®r
• Type: Class ABr

Specifications of LM4936MH/NOPB

• Output Type: 2-Channel (Stereo) with Stereo Headphones
• Max Output Power X Channels @ Load: 2.2W x 2 @ 3 Ohm; 110mW x 2 @ 32 Ohm
• Voltage - Supply: 2.7 V ~ 5.5 V
• Features: Bass Boost, Depop, I²C, Mute, Shutdown, SPI, Thermal Protection, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
• For Use With: LM4936MHEVAL - BOARD EVALUATION LM4936MH
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM4936MH; *LM4936MH/NOPB; *LM4936MHNOPB; LM4936MH; LM4936MHNOPB; LM4936MHNOPB; LM4936MN/NOPB

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Application Information
SPI OPERATIONAL REQUIREMENTS
1. The maximum clock rate is 5MHz for the CLK pin.
2. CLK must remain logic-high for at least 100ns (t
the rising edge of CLK, and CLK must remain logic-low for at
least 100ns (t
3. Data bits are written to the DATA pin with the most
significant bit (MSB) first.
4. The serial data bits are sampled at the rising edge of CLK.
Any transition on DATA must occur at least 50ns (t
the rising edge of CLK. Also, any transition on DATA must
occur at least 50ns (t
stabilize before the next rising edge of CLK.
5. ENABLE should be logic-low only during serial data trans-
mission.
CL
) after the falling edge of CLK.
DH
) after the rising edge of CLK and
(Continued)
DS
CH
) before
) after
FIGURE 4.
24
SPI TIMING DIAGRAM
6. ENABLE must be logic-low at least 50ns (t
first rising edge of CLK, and ENABLE has to remain logic-
low at least 50ns (t
7. If ENABLE remains logic-high for more than 50ns before
all 8 bits are transmitted then the data latch will be aborted.
8. If ENABLE is logic-low for more than 8 CLK pulses then
only the first 8 data bits will be latched and activated at rising
edge of eighth CLK.
9. ENABLE must remain logic-high for at least 50ns (t
10. Coincidental rising or falling edges of CLK and ENABLE
are not allowed. If CLK is to be held logic-high after the data
transmission, the falling edge of CLK must occur at least
50ns (t
next set of data.
CS
) before ENABLE transitions to logic-low for the
EH
) after the eighth rising edge of CLK.
20117823
ES
) before the
EL
).