LMV1090TL/NOPB National Semiconductor, LMV1090TL/NOPB Datasheet - Page 15

• Manufacturer Part Number: LMV1090TL/NOPB
• Description: IC AMP MIC DUAL INPUT 16USMD
• Manufacturer: National Semiconductor
• Series: PowerWise®r
• Type: Class ABr

Specifications of LMV1090TL/NOPB

• Output Type: 2-Channel (Stereo)
• Voltage - Supply: 2.7 V ~ 5.5 V
• Features: Differential Inputs, Microphone, Shutdown
• Mounting Type: Surface Mount
• Package / Case: 16-MicroSMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Max Output Power X Channels @ Load: -
• Lead Free Status / Rohs Status: Details
• Other names: LMV1090TLTR

Example 2
An application using microphones with 10mV
output voltage, and a baseband chip after the LMV1090 with
3.3V
For optimum noise performance we would like to have the
maximum gain at the input stage.
1.
2.
3.
4.
5.
So using preamp gain = 36dB and postamp gain = 6dB is
optimum for this application.
I
The LMV1090 is controlled through an I
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock line are uni-directional. *The LMV1090
and the master can communicate at clock rates up to 400kHz.
Figure 5 shows the I
SDA line must be stable during the HIGH period of SCL. The
LMV1090 is a transmit/receive slave-only device, reliant upon
the master to generate the SCL signal. Each transmission
sequence is framed by a START condition and a STOP con-
dition (Figure 6). The data line is 8 bits long and is always
followed by an acknowledge pulse (Figure 7).
I
Supply Pin (I
The LMV1090 I
I
*The data line is bi-directional (open drain)
2
2
2
CV
C Compatible Interface
C Compatible Interface Power
P-P
10mV
This is lower than the maximum 1.5V
The NCB has a gain of 0dB which will result in 1.5V
the output of the LMV1091. This level is lower than
maximum level that is allowed at the input of the Post
Amp of the LMV1091.
With a Post Amp gain setting of 6dB the output of the
Post Amp will be 3V
The nearest lower Post Amp gain will be 6dB.
DD
pin. The LMV1090 I
maximum input voltage.
P-P
+ 36dB = 631mV
2
C interface is powered up through the
2
C Interface timing diagram. Data on the
2
CV
P-P
2
DD
which is OK for the baseband.
C interface operates at a voltage
P-P
)
.
2
C compatible serial
P-P
so this is OK.
P-P
FIGURE 5. I
maximum
P-P
at
2
C Timing Diagram
15
level set by the I
that of the main power supply pin V
logic levels for the I
troller or microprocessor that is operating at a lower supply
voltage than the main battery of a portable system.
I
The I
the transition of SDA from HIGH to LOW while SCL is HIGH
is generated, alerting all devices on the bus that a device ad-
dress is being written to the bus. The 7-bit device address is
written to the bus, most significant bit (MSB) first followed by
the R/W bit, R/W = 0 indicates the master is writing to the slave
device, R/W = 1 indicates the master wants to read data from
the slave device. Set R/W = 0; the LMV1090 is a WRITE-
ONLY device and will not respond to the R/W = 1. The data
is latched in on the rising edge of the clock. Each address bit
must be stable while SCL is HIGH. After the last address bit
is transmitted, the mater device release SDA, during which
time, an acknowledge clock pulse is generated by the slave
device. If the LMV1090 receives the correct address, the de-
vice pulls the SDA line low, generating an acknowledge bit
(ACK)
Once the master device registers the ACK bit, the 8-bit reg-
ister data word is sent. Each data bit should be stable while
SCL is HIGH. After the 8-bit register data word is sent, the
LMV1090 sends another ACK bit. Following the acknowl-
edgement of the last register data word, the master issues a
STOP bit, allowing SDA to go high while SCL is high.
2
C Bus Format
2
C bus format is shown in Figure 7. The START signal,
2
CV
2
DD
C Interface are dictated by a microcon-
pin which can be set independent to
DD
. This is ideal whenever
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