ADRF6602ACPZ-R7 Analog Devices Inc, ADRF6602ACPZ-R7 Datasheet - Page 22

• Manufacturer Part Number: ADRF6602ACPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of ADRF6602ACPZ-R7

• Lead Free Status / Rohs Status: Compliant

ADRF6602
APPLICATIONS INFORMATION
BASIC CONNECTIONS FOR OPERATION
Figure 46 shows the schematic for the ADRF6602 evaluation
board. The six power supply pins should be individually decoupled
using 100 pF and 0.1 μF capacitors located as close as possible
to the device. In addition, the internal decoupling nodes
(DECL3P3, DECL2P5, and DECLVCO) should be decoupled
with the capacitor values shown in Figure 46.
The RF input is internally ac-coupled and needs no external
bias. The IF outputs are open collector, and a bias inductor is
required from these outputs to VCC.
A peak-to-peak differential swing on RF
for a sine wave input) results in an IF output power of 3.8 dBm.
The reference frequency for the PLL should be from 12 MHz to
160 MHz and should be applied to the REF_IN pin, which should
OPEN
LO IN/OUT
(0402)
S1
VCC1
RED
R56
0Ω
REFOUT
REF_IN
R55
OPEN
(0402)
TC1-1-13+
(0402)
49.9Ω
4
5
R70
T8
(0402)
R16
0Ω
3
1
(0402)
C31
1nF
LODRV_EN
(0402)
(0402)
1nF
1nF
C5
C6
MUXOUT
REF_IN
LON
LOP
36
37
38
VCC_LO
6
8
VCC
RED
+5V
ADRF6602
÷2
÷4
×2
34
R6
0Ω
(0402)
VCC_V2I
C7
0.1µF
(0402)
C8
100pF
(0402)
MUX
4
27
7 11 15 20 21 23 24 25 28 30 31 35
R26
0Ω
(0402)
FRACTION
SENSOR
VCC_MIX
TEMP
INTERPOLATOR
C25
0.1µF
(0402)
C24
100pF
(0402)
THIRD-ORDER
REG
FRACTIONAL
IN
of 1 V (0.353 V rms
Figure 46. Basic Connections for Operation of the ADRF6602
22
(ORANGE)
R25
0Ω
(0402)
MODULUS INTEGER
VCC_LO
C23
0.1µF
(0402)
C22
100pF
(0402)
POINT
–
+
TEST
FREQUENCY
DETECTOR
CP
N COUNTER
PHASE
21 TO 123
17
R25
0Ω
(0402)
(0603)
(0402)
22pF
(0603)
R38
C14
10µF
0Ω
C20
0.1µF
(0402)
C21
100pF
(0402)
REG
C43
VCC2
(0402)
R37
10
0Ω
R11
OPEN
(0402)
Rev. C | Page 22 of 32
OPEN
(0402)
R17
0Ω
(0402)
PRESCALER
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
R9 10kΩ
R SET
OPEN
(0402)
(0402)
C2
R10
3.0kΩ
(0603)
C19
0.1µF
(0402)
C18
100pF
(0402)
C15
2.7nF
(1206)
S2
VCC1
R2
VCC
÷2
(0402)
5
R1
0Ω
R54
10kΩ
(0402)
100pF
(0402)
1
R65 10kΩ
(0402)
R7
0Ω
(0402)
C13
6.8pF
(0603)
C1
BUFFER
BUFFER
(0402)
10kΩ
C9
0.1µF
(0402)
C10
100pF
(0402)
R53
be ac-coupled and terminated with a 50 Ω resistor as shown
in Figure 46. The reference signal, or a divided-down version o
the reference signal, can be brought back off chip at the multiplexer
output pin (MUXOUT). A lock detect signal and a voltage
proportional to the ambient temperature can also be selected
on the multiplexer output pin.
The loop filter is connected between the CP and VTUNE pins.
When connected in this way, the internal VCO is operational.
For information about the loop filter components, see
the Evaluation Board Configuration Options sectio
Operation with an external VCO is also possible. In this case,
the loop filter components should be referred to ground. The
output of the loop filter is connected to the input voltage pin of
the external VCO. The output of the VCO is brought back into
the device on the LOP and LON pins, using a balun if necessary.
(0402)
R12
0Ω
(0402)
R20
C40
22pF
(0603)
0Ω
3
CP
MUX
2:1
(0402)
CORE
VCO
R19
39
0Ω
VTUNE
1
DIVIDER
R62
0Ω
(0402)
2
÷2
2, 1
DIV
BY
3
40
R35
0Ω
(0402)
DECLVCO
OPEN
(0402)
4
R63
5
VTUNE
6
R30
0Ω
(0402)
16
7
INTERFACE
13
IFP
8
SPI
R57
0Ω
(0402)
12
18
9
VCC
+5V
14
19
P1
9-PIN
DSUB
IFN
R36
0Ω
(0402)
26
29
9
2
(0402)
C29
0.1µF
(0402)
C34
OPEN
(0402)
C33
OPEN
(0402)
C32
OPEN
(0402)
DECL2P5
DECL3P3
R59
RF IN
IP3SET
0Ω
1
2
3
(0402)
R28
(0402)
R51
OPEN
(0402)
R50
OPEN
(0402)
R52
OPEN
(0402)
0Ω
R27
0Ω
4
5
C16
100pF
(0402)
C12
100pF
(0402)
(0402)
R43
0Ω
(0402)
(0402)
R18
0Ω
0Ω
R8
RFIN
C27
0.1µF
(0402)
RFOUT
C17
0.1µF
(0402)
C11
0.1µF
(0402)
n.
C42
10µF
(0603)
C41
OPEN
(0603)
f