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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Up Counters
are constructed with MOS P–channel and N–channel enhancement mode
devices in a single monolithic structure. Each consists of two identical,
independent, internally synchronous 4–stage counters. The counter stages
are type D flip–flops, with interchangeable Clock and Enable lines for
incrementing on either the positive–going or negative–going transition as
required when cascading multiple stages. Each counter can be cleared by
applying a high level on the Reset line. In addition, the MC14518B will count
out of all undefined states within two clock periods. These complementary
MOS up counters find primary use in multi–stage synchronous or ripple
counting applications requiring low power dissipation and/or high noise
immunity.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
REV 3
1/94
MAXIMUM RATINGS*
V in , V out
Symbol
MOTOROLA CMOS LOGIC DATA
I in , I out
The MC14518B dual BCD counter and the MC14520B dual binary counter
Motorola, Inc. 1995
V DD
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Internal and External Speeds
Logic Edge–Clocked Design — Incremented on Positive Transition of
Clock or Negative Transition on Enable
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
T stg
P D
T L
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic “L” Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
X = Don’t Care
Clock
X
X
0
1
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
Lead Temperature (8–Second Soldering)
Enable
1
X
0
X
TRUTH TABLE
(Voltages Referenced to V SS )
Parameter
Reset
0
0
0
0
0
0
1
Increment Counter
Increment Counter
Q0 thru Q3 = 0
No Change
No Change
No Change
No Change
Action
0.5 to V DD + 0.5
– 0.5 to + 18.0
– 65 to + 150
Value
500
260
10
Unit
mW
mA
_ C
_ C
V
V
ENABLE
ENABLE
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, V in and V out should be constrained
to the range V SS
appropriate logic voltage level (e.g., either V SS
or V DD ). Unused outputs must be left open.
CLOCK
CLOCK
This device contains protection circuitry to
Unused inputs must always be tied to an
T A = – 55 to 125 C for all packages.
10
15
1
2
7
9
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
MC14518B
MC14520B
BLOCK DIAGRAM
v
MC14518B MC14520B
(V in or V out )
DW SUFFIX
CASE 751G
CERAMIC
CASE 620
CASE 648
V DD = PIN 16
L SUFFIX
P SUFFIX
PLASTIC
V SS = PIN 8
Plastic
Ceramic
SOIC
C
C
SOIC
v
R
R
V DD .
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
409
3
4
5
6
11
12
13
14