HT48R50A-1 Holtek, HT48R50A-1 Datasheet
HT48R50A-1
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HT48R50A-1 Summary of contents
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... Watchdog Timer General Description The HT48R50A-1/HT48C50-1 are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for multiple I/O control product applications. The mask version HT48C50-1 is fully pin and functionally compatible with the OTP version HT48R50A-1 device ...
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... Block Diagram Rev. 2.00 HT48R50A-1/HT48C50-1 2 March 8, 2006 ...
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... PC0~PC7 I/O Pull-high* TMR1 I Rev. 2.00 HT48R50A-1/HT48C50-1 Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by options. Software instructions determine the CMOS out- put or Schmitt trigger or CMOS input with pull-high resistor (determined by pull-high option). Bidirectional 8-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high option) ...
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... Low Voltage Reset LVR I I/O Port Sink Current OL Rev. 2.00 HT48R50A-1/HT48C50-1 Description Schmitt trigger reset input. Active low Positive power supply OSC1, OSC2 are connected network or Crystal (determined by option) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock. These two pins can also be optioned as an RTC oscillator (32768Hz) or I/O lines ...
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... Watchdog Time-out Period t WDT3 (RTC OSC) External Reset Low Pulse t RES Width t System Start-up Timer Period SST t Interrupt Pulse Width INT Note 1/f , 1/f or 1/f SYS SYS1 SYS2 SYS3 Rev. 2.00 HT48R50A-1/HT48C50-1 Test Conditions Min. V Conditions =0. =0. Test Conditions Min. V Conditions DD 2 ...
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... Return from Subroutine S11 Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 2.00 HT48R50A-1/HT48C50-1 When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call, initial re- set, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction ...
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... Note: *11~*0: Table location bits @7~@0: Table pointer bits Rev. 2.00 HT48R50A-1/HT48C50-1 Table location Any location in the ROM space can be used as look-up tables. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H) ...
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... Writing indirectly results in no operation. The memory pointer registers (MP0 and MP1) are 8-bit registers. Rev. 2.00 HT48R50A-1/HT48C50-1 RAM Mapping Accumulator The accumulator is closely related to ALU operations also mapped to location 05H of the data memory and can carry out immediate data operations ...
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... TO is set by a WDT time-out. 6~7 Unused bit, read as 0 Rev. 2.00 HT48R50A-1/HT48C50-1 rupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related in- terrupt is enabled, until the SP is decremented ...
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... If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be dam- aged once the CALL operates in the interrupt subrou- tine. Rev. 2.00 HT48R50A-1/HT48C50-1 Function INTC (0BH) Register Oscillator configuration There are 3 oscillator circuits in the microcontroller. ...
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... If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) or 32kHz crystal oscilla- tor (RTC OSC) is strongly recommended, since the HALT will stop the system clock. Rev. 2.00 HT48R50A-1/HT48C50-1 WS2 WS1 WS0 ...
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... Most registers are reset to the initial condition when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets . Rev. 2.00 HT48R50A-1/HT48C50-1 Reset Timing Chart Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference ...
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... PDC 1111 1111 PG ---- -111 PGC ---- -111 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 2.00 HT48R50A-1/HT48C50-1 RES Reset (Normal Operation) xxxx xxxx xxxx xxxx 00-0 1000 00-0 1000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 00-0 1--- ...
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... T1M1 11=Pulse width measurement mode 00=Unused Rev. 2.00 HT48R50A-1/HT48C50-1 (can always be optioned tem oscillator in the Int. RC+RTC mode) by options. Using external clock input allows the user to count exter- nal events, measure time internals or pulse widths, or generate an accurate time base. While using the inter- nal clock allows the user to generate an accurate time base ...
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... Timer/Event Counter 0/1 preload register and generates the interrupt request flag (T0F/T1F; bit 5/6 of INTC) at the same time. Rev. 2.00 HT48R50A-1/HT48C50-1 In the pulse width measurement mode with the T0ON/T1ON and T0E/T1E bits equal to one, once the TMR0/TMR1 has received a transient from low to high ...
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... If the control register bit the contents of the latches will move to the internal bus. The latter is possi- ble in the read-modify-write instruction. Rev. 2.00 HT48R50A-1/HT48C50-1 For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H, 17H, 19H and 1FH. ...
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... To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before starting the normal operation. *2: Since low voltage has to be maintained its original state for longer than 1ms, therefore a 1ms delay enters the reset mode. Rev. 2.00 HT48R50A-1/HT48C50 ...
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... PA, PB, PC, PD, PG pull-high enable or disable (By port) 8 BZ/BZ enable or disable 9 LVR enable or disable System oscillator 10 Ext. RC, Ext.crystal, Int.RC+RTC or Int.RC+PG1/PG2 11 Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz Rev. 2.00 HT48R50A-1/HT48C50-1 Options /4 or RTC oscillator or disable SYS or RTCOSC SYS /4 or RTCOSC SYS 18 March 8, 2006 ...
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... The function of the resistor ensure that the oscillator will switch off should low voltage condi- tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Rev. 2.00 HT48R50A-1/HT48C50-1 C1, C2 0pF 10pF ...
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... Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 2.00 HT48R50A-1/HT48C50-1 Description 20 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 2.00 HT48R50A-1/HT48C50-1 Description 21 Instruction Flag Cycle Affected 2 None ...
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... ACC ACC+x Affected flag(s) TO ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF PDF PDF PDF OV ...
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... The indicated address is then loaded. Program execution continues with the instruction at this address. Operation Stack Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF PDF PDF addr PDF ...
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... WDT 00H* PDF and TO Affected flag( CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF PDF PDF ...
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... Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF ...
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... The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation Program Counter Affected flag(s) TO MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 Program Counter+1 PDF PDF PDF addr ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF PDF Program Counter+1 PDF ...
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... Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 Stack PDF Stack PDF OV Z ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF OV ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF PDF OV Z ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF PDF ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF PDF PDF ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF PDF PDF ...
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... XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 2.00 HT48R50A-1/HT48C50-1 PDF PDF PDF OV ...
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... Package Information 28-pin SKDIP (300mil) Outline Dimensions Symbol Rev. 2.00 HT48R50A-1/HT48C50-1 Dimensions in mil Min. Nom. 1375 278 125 125 16 50 100 295 330 0 35 Max. 1395 298 135 145 20 70 315 375 15 March 8, 2006 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 2.00 HT48R50A-1/HT48C50-1 Dimensions in mil Min. Nom. 394 290 14 697 Max. 419 300 20 713 104 March 8, 2006 ...
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... SSOP (300mil) Outline Dimensions Symbol Rev. 2.00 HT48R50A-1/HT48C50-1 Dimensions in mil Min. Nom. 395 291 8 613 Max. 420 299 12 637 March 8, 2006 ...
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... Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.00 HT48R50A-1/HT48C50-1 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1.0 100 0.1 13.0+0.5 ...
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... Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 HT48R50A-1/HT48C50-1 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.85 0.1 18.34 0.1 2.97 0.1 ...
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... A0 Cavity Length B0 Cavity Width K1 Cavity Depth K2 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 HT48R50A-1/HT48C50-1 Dimensions in mm 32.0 0.3 16.0 0.1 1.75 0.1 14.2 0.1 2.0 Min. 1.5+0.25 4.0 0.1 2.0 0.1 12.0 0.1 16.20 0.1 2.4 0.1 3.2 0.1 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.00 HT48R50A-1/HT48C50-1 41 March 8, 2006 ...