AD6472BS Analog Devices, AD6472BS Datasheet
AD6472BS
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AD6472BS Summary of contents
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... LOGIC 12-BIT ADC REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
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AD6472–SPECIFICATIONS P arameter TRANSMIT CHANNEL SNR THD TRANSMIT DAC Clock Frequency Resolution Update Rate Output Voltage TRANSMIT FILTER 1 Corner Frequency (3 dB) Accuracy Gain LINE DRIVER VCM Output Power Output Voltage TRANSMIT VOLTAGE LEVEL RECEIVE CHANNEL SNR THD HYBRID ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics 80-Lead Plastic Quad Flatpack Package . . . . . . . Temperature Model Range AD6472BS – +85 C +5V_DVDD DGND MODE_SEL0 MODE_SEL1 AA_FLTR_BP PWRDN ...
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AD6472 Pin Mnemonic Description 1 +5 V_DVDD +5 V Digital Supply. 2 DGND Digital Ground. 3 MODE_SEL0 Bit Rate—Filter Corner Select. 4 MODE_SEL1 Bit Rate—Filter Corner Select. 5 AA_FLTR_BP Antialiasing Filter Bypass. PWRDN 6 Power-Down Active Low ...
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Circuit Description The AD6472 is an HDSL analog front end for either 2-pair or single pair applications. Transmit Channel The AD6472 receives, from a DSP transceiver core, a serial 2s complement data stream. The data are 16-bit words and the ...
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AD6472 Receive Channel Hybrid Amplifier The hybrid amplifier performs balanced to unbalanced conversion. Programmable Gain Amplifier (PGA) The PGA can be programmed to amplify the receive signal from between –6 dB and 9 dB. Refer to Table II for PGA ...
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S1 ANALOG INPUT INPUT CLOCK RXCLK OUTPUT DATA RX11:RX0 Receive Interface Timing The analog input is sampled at the rising edge of the RXCLK. The digital data, RX11:RX0, is valid on each falling edge of RXCLK. ...
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AD6472 t 12ns SU t 10ns H SCLK 1 SFRAME D6 SDATA D5 D4 MSB 1. THE RISING EDGE OF SFRAME CAN OCCUR ANYWHERE. SFRAME MUST BE AT LEAST ONE CLOCK CYCLE WIDE. 2. SFRAME FALLING EDGE MUST OCCUR BEFORE ...