M36D0R6040T0ZAI STMicroelectronics, M36D0R6040T0ZAI Datasheet

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M36D0R6040T0ZAI

Manufacturer Part Number
M36D0R6040T0ZAI
Description
64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
Manufacturer
STMicroelectronics
Datasheet

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FEATURES SUMMARY
FLASH MEMORY
December 2004
MULTI-CHIP PACKAGE
SUPPLY VOLTAGE
LOW POWER CONSUMPTION
ELECTRONIC SIGNATURE
PACKAGE
PROGRAMMING TIME
MEMORY BLOCKS
ASYNCHRONOUS READ
DUAL OPERATIONS
BLOCK LOCKING
1 die of 64 Mbit (4Mb x 16) Flash Memory
1 die of 16 Mbit (1Mb x 16) Pseudo SRAM
V
Manufacturer Code: 20h
Device Code (Top Flash Configuration),
M36D0R6040T0: 8810h
Device Code (Bottom Flash
Configuration), M36D0R6040B0: 8811h
Compliant with Lead-Free Soldering
Processes
Lead-Free Versions
8µs by Word typical for Fast Factory
Program
Double/Quadruple Word Program option
Enhanced Factory Program options
Multiple Bank Memory Array: 4 Mbit
Banks
Parameter Blocks (Top location)
Asynchronous Page Read mode
Random Access: 70ns
Program Erase in one Bank while Read in
others
No delay between Read and Write
operations
All blocks locked at Power-up
Any combination of blocks can be locked
WP
DDF
F
for Block Lock-Down
= V
64 Mbit (4Mb x16, Multiple Bank, Page) Flash Memory
DDP
and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package
= 1.7V to 1.95V
Figure 1. Package
PSRAM
SECURITY
COMMON FLASH INTERFACE (CFI)
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ACCESS TIME: 70ns
LOW STANDBY CURRENT: 110µA
DEEP POWER DOWN CURRENT: 10µA
128-bit user programmable OTP cells
64-bit unique device number
Stacked TFBGA67 (ZAI)
M36D0R6040B0
M36D0R6040T0
12 x 8mm
FBGA
1/18

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M36D0R6040T0ZAI Summary of contents

Page 1

Mbit (4Mb x16, Multiple Bank, Page) Flash Memory and 16 Mbit (1Mb x16) PSRAM, Multi-Chip Package FEATURES SUMMARY MULTI-CHIP PACKAGE – 1 die of 64 Mbit (4Mb x 16) Flash Memory – 1 die of 16 Mbit (1Mb x ...

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M36D0R6040T0, M36D0R6040B0 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table 5. AC Measurement Load Circuit ...

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M36D0R6040T0, M36D0R6040B0 SUMMARY DESCRIPTION The M36D0R6040T0 and M36D0R6040B0 com- bine two memory devices in a Multi-Chip Package: a 64-Mbit, Multiple Bank Flash memory, the M58WR064FT/B, and a 16-Mbit Pseudo SRAM, the M69AR024B. Recommended operating condi- tions do not allow more ...

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Figure 3. TFBGA Connections (Top view through package) M36D0R6040T0, M36D0R6040B0 5/18 ...

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M36D0R6040T0, M36D0R6040B0 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram Names, for a brief overview of the signals connect this device. Address Inputs (A0-A19). Addresses are common inputs for the Flash Memory and PSRAM components. The Address Inputs select ...

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kept in a low voltage range ( PPF V is seen as a control input. In this case a volt- PPF age lower than V gives an absolute protec- PPLKF tion against Program or Erase, ...

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M36D0R6040T0, M36D0R6040B0 FUNCTIONAL DESCRIPTION The Flash memory and PSRAM components have separate power supplies but share the same grounds. They are distinguished by three Chip En- able inputs: E for the Flash memory and for the PSRAM. ...

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Table 2. Main Operating modes Operation Flash Read Flash Write Flash Address Latch Flash Output ...

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... PSRAM. For detailed information on how to use it, see the M69AR024B datasheet 10/18 For detailed information on how to use the Flash memory, see the M58WR064F(T/B) datasheet which is available from your local STMicroelec- tronics distributor. which is available from the internet site http:// www.st.com or from your local STMicroelectronics distributor. ...

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... Compliant with the JEDEC Std J-STD-020B (for small body, Sn- assembly), the ST ECOPACK and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU. plied. Exposure to Absolute Maximum Rating con- ditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality docu- ments. Parameter ...

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M36D0R6040T0, M36D0R6040B0 DC AND AC PARAMETERS This section summarizes the operating measure- ment conditions, and the DC and AC characteris- tics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed ...

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Table 7. Flash Memory DC Characteristics - Currents Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO Supply Current I DD1 Asynchronous Read (f=6MHz) Supply Current I DD2 (Reset) I Supply Current (Standby) DD3 Supply Current (Automatic ...

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M36D0R6040T0, M36D0R6040B0 Table 9. PSRAM DC Characteristics Symbol Parameter I CC1 V Active Current CC I CC2 I Input Leakage Current LI I Output Leakage Current LO I Deep Power Down Current PD Standby Supply Current I SB CMOS (1) ...

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PACKAGE MECHANICAL Figure 6. Stacked TFBGA67 12x8mm - 8x8 active ball array, 0.8mm pitch, Package Outline BALL "A1" FE FD1 FD A Note: Drawing is not to scale. Table 10. Stacked TFBGA67 12x8mm - 8x8 ball array, ...

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M36D0R6040T0, M36D0R6040B0 PART NUMBERING Table 11. Ordering Information Scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture D = Multiple Bank, Page mode Flash 2 Architecture 0 = none present Operating Voltage ...

Page 17

REVISION HISTORY Table 12. Document Revision History Date Version 26-Nov-2003 1.0 First Issue Document status promoted from Target Specification to full Datasheet. TFBGA67 package fully compliant with the ST ECOPACK specification. 07-Dec-2003 2.0 Flash memory and PSRAM data updated to ...

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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...

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