SAB82532N-10 Siemens Semiconductor Group, SAB82532N-10 Datasheet
SAB82532N-10
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SAB82532N-10 Summary of contents
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ICs for Communications Enhanced Serial Communication Controller ESCC2 SAB 82532 SAF 82532 Version 3.2 User’s Manual 07.96 ...
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SAB 82532 SAF 82532 Revision History: Previous Version: User’s Manual 07.93 Page Page (in previous (in new Version) Version 110, 141, 167 124, 170, 208 Timer register (TIMR): description extended for V3.x ...
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Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 5.4.8 One Bit Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 9.3 Operational Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Introduction The Enhanced Serial Communication Controller ESCC2 (SAB 82532/SAF 82532 multiprotocol data communication controller with two symmetrical serial channels. It has been designed to implement high-speed communication links and to reduce hardware and software overhead needed for ...
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Enhanced Serial Communication Controller ESCC2 1.1 Features Serial Interface • Two independent full duplex serial channels – On chip clock generation or external clock source – On chip DPLL for clock recovery of each channel – Two independent baud rate ...
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Support of bus configuration by collision detection and resolution • Statistical multiplexing • Continuous transmission bytes possible • Programmable preamble (8 bit) with selectable repetition rate (HDLC/SDLC and BISYNC) • Data rate ...
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Pin Configuration (top view) Figure 1 Semiconductor Group SAB 82532/SAF 82532 P-LCC-68 9 Introduction 07.96 ...
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Figure 2 Semiconductor Group SAB 82532/SAF 82532 P-MQFP-80-1 10 Introduction 07.96 ...
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Pin Definitions and Functions Pin No. P-LCC-68 P-MQFP-80 2 ... 8 31 … ... 45 19 … Note: All unused input pins have to be connected to a defined level. Semiconductor Group Symbol Input ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) RD/DS I Read Enable (Siemens/Intel bus mode) This signal indicates a read operation. When the ESCC2 ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) RES I Reset A high signal on this pin forces the ESCC2 into reset state. During ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) DTACK O (oD) Data Transfer Acknowledge During a bus cycle (read/write, asynchronous bus), this signal indicates that ESCC2 ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) INTA I Interrupt Acknowledge If the interrupt is acknowledged via pin INTA, an interrupt vector is output on D0 … ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) IE0 I/O Interrupt Enable 0, 1 IE1 I The function depends on the selected cascading mode: Slave mode: ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) DRTA O DMA Request Transmitter DRTB (channel A/channel B) The transmitter of ESCC2 requests ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) DACKA I DMA Acknowledge DACKB (channel A/channel B) A low ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) RTSA O Request to Send RTSB (channel A/channel B) When the RTS bit in ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) CDA I Carrier Detect CDB (channel A/channel B) The function of this pin depends ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP- Semiconductor Group Symbol Input (I) Function Output (O) TxCLKA I/O Transmit Clock TxCLKB (channel A/channel B) The function of this pin depends ...
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Pin Definitions and Functions (cont’d) Pin No. P-LCC-68 P-MQFP-80 62 ... 68,1 23 … 21, 22, 65 61, 62 Note: All unused input pins have to be connected to a defined level. Semiconductor Group ...
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Logic Symbol Figure 3 ESCC2 Logic Symbol Semiconductor Group SAB 82532/SAF 82532 23 Introduction 07.96 ...
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Functional Block Diagram Figure 4 Functional Block Diagram SAB 82532/SAF 82532 The ESCC2 (SAB 82532/SAF 82532) comprises two completely independent full-duplex serial interfaces (channel A and channel B) which support HDLC/SDLC, BISYNC and ASYNC protocols. Layer-1 functions are performed ...
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System Integration 1.6.1 General Aspects Figure 5 General System Integration of ESCC2 Figure 5 gives a general overview of system integration of ESCC2. The ESCC2’s bus interface consists of an 8/16-bit bidirectional data bus (D0 … D15), seven Address ...
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Environment 1.6.2.1 ESCC2 with SAB 8051 Microcontroller For cost-sensitive applications, the ESCC2 can be interfaced with a small 8051 microcontroller system (without DMA support) very easily as shown in figure 6. Figure 6 ESCC2 with SAB 8051 CPU Although ...
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ESCC2 with SAB 80188 Microprocessor A system with minimized additional hardware expense can be build up with a SAB 80188 microprocessor as shown in figure 7. Figure 7 ESCC2 with SAB 80188 CPU The ESCC2 is connected to the ...
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ESCC2 with SAB 80286 Microprocessor and SAB 82258 Advanced DMA Controller (ADMA) In applications where two high-speed channels are required, a 16-bit system with 80286 CPU and 82258 Advanced DMA controller (ADMA) is suitable. This is shown in figure ...
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Another significant advantage of the ADMA is its Data Chaining feature, providing an optimized memory management for receive and transmit data. Recording the ESCC2, a linked chain of 32 byte deep buffers can be set up, which are subsequently filled ...
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ESCC2 with MC 68008 Figure 9 gives an overview for connecting the ESCC2 to the Motorola type microprocessor MC 68008. Interfacing is very simple because most lines can be connected directly. Figure 9 ESCC2 with MC 68008 Semiconductor Group ...
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ESCC2 with MC 68000, 68010, 68012 In these 16-bit systems the integration of some additional glue logic is necessary (refer to figure 10). The reason is that these microprocessors provide two different data strobe signals for low byte/high byte ...
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ESCC2 with MC 68020, 68030 Figure 11 gives an example of interfacing to a 32-bit Motorola microprocessor. As for MC 68000, 68010 and 68012 microprocessors, some glue logic is necessary, too. The signal Bus Low Enable (BLE) has to ...
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Interrupt Cascading The ESCC2 supports two cascading schemes which can be selected by programming the IPC register: Slave Mode Interrupt outputs of several devices (slaves) are connected to a priority resolving unit (e.g. interrupt controller). The slave which is ...
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Figure 13 Interrupt Cascading (slave mode) in Motorola Bus Mode Semiconductor Group SAB 82532/SAF 82532 34 Introduction 07.96 ...
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Daisy Chaining If selected via IPC register the Interrupt Enable pins IE0, IE1 are used for building a Daisy Chain by connecting the Interrupt Enable Output (IE0) of the higher priority device to the Interrupt Enable Input (IE1) of the ...
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Figure 15 Interrupt Cascading (Daisy Chaining) in Motorola Bus Mode For Motorola type microprocessor systems the maximum available settling time for the chain is much shorter: from the beginning of the INTA cycle to the falling edge of signal DS. ...
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Basic Functional Principles 2.1 General The ESCC2 distinguishes itself from other communication controllers by its advanced characteristics. The most important are: – Support of HDLC, SDLC, BISYNC/MONOSYNC and Asynchronous protocols – Support of layer-2 functions (HDLC mode) In addition ...
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Telecom specific features In a special operating mode, the ESCC2 can transmit or receive data packets in one time-slots of programmable width (clock mode 5). Furthermore, the ESCC2 can transmit or receive variable data portions ...
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Link Configurations Figure 16a Point-to-Point Configuration Figure 16b Point-to-Multipoint Configuration Figure 16c Multimaster Configuration Semiconductor Group SAB 82532/SAF 82532 Basic Functional Principles 39 07.96 ...
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FIFO Structure In both transmit and receive direction 64-byte deep FIFO’s are provided for the intermediate storage of data between the serial interface and the CPU interface. The FIFO’s are divided into two halves of 32-bytes. Only one half ...
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Figure 18 FIFO Word Access (Motorola mode) Semiconductor Group SAB 82532/SAF 82532 Basic Functional Principles 41 07.96 ...
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Microprocessor Interface 3.1 Register Set The communication between the CPU and the ESCC2 is done via a set of directly accessible registers. The interface may be configured as Siemens/Intel or Motorola type with a selectable data bus width of ...
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Table 2 Data Bus Access (16-bit Motorola mode) BHE A0 Register Access 0 0 FIFO word access Register word access (even addresses Register byte access (odd addresses Register byte access (odd addresses transfer ...
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Data Transfer Modes Data transfer between the system memory and the ESCC2 for both transmit and receive direction is controlled by either interrupts (interrupt mode), or independently from CPU, using the ESCC2’s 4-channel DMA interface (DMA mode). After RESET, ...
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Each interrupt indication of registers ISR0, ISR1 and PIS can be selectively masked by setting the corresponding bit in the corresponding mask registers IMR0, IMR1 and PIM. Use of these registers depends on the selected serial mode. GIS, the non-maskable ...
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Figure 20 Structure of Interrupt Vector In case more than one source is active, the generated vector refers to the active group with highest priority (group 1 has highest, group 8 lowest priority). Interrupt groups are assigned ...
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Masked Interrupts Visible in Status Registers (version 2 upward) The interrupt vector contains only one interrupt at a time: the interrupt displayed in this vector results from a priority resolution among all unmasked active interrupt statuses. The Global Interrupt Status ...
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DMA Interface The ESCC2 comprises a 4-channel DMA interface for fast and efficient data transfers. For both serial channels, a separate DMA Request output for transmit (DRT) and receive direction (DRR) as well as a DMA Acknowledgement (DACK) input ...
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HDLC/SDLC Serial Mode 5.1 Operating Modes The HDLC controller of each channel can be programmed to operate in various modes, which are different in the treatment of the HDLC frame in receive direction. Thus, the receive data flow and ...
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Non-Auto-Mode (MODE: MDS1, MDS0 = ‘01’) Characteristics: address recognition, arbitrary window size. All frames with valid addresses (address recognition identical to auto-mode) are forwarded directly via the RFIFO to the system memory. The HDLC control field, data in the I-field ...
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Receive Data Flow (summary) The following figure gives an overview of the management of the received HDLC frames in the different operating modes. Figure 22 Receive Data Flow of ESCC2 Semiconductor Group SAB 82532/SAF 82532 HDLC/SDLC Serial Mode 51 07.96 ...
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Transmit Data Flow Two different types of frames can be transmitted: – I-frames and – transparent frames as shown below. Figure 23 Transmit Data Flow of ESCC2 For I-frames (command XIF via CMDR register), the address and control fields are ...
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Procedural Support (layer-2 functions) When operating in the auto mode, the ESCC2 offers a high degree of protocol support. In addition to address recognition, the ESCC2 autonomously processes all (numbered) S- and I-frames (prerequisite window size 1) with either ...
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Figure 24 Processing of Received Frames in Auto Mode Semiconductor Group SAB 82532/SAF 82532 HDLC/SDLC Serial Mode 54 07.96 ...
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Transmission of Frames The ESCC2 autonomously transmits S commands and S responses in the auto mode. Either transparent or I-frames can be transmitted by the user. The software timer has to be operated in the internal timer mode to transmit ...
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Figure 25 Timer Procedure/Poll Cycle Semiconductor Group SAB 82532/SAF 82532 HDLC/SDLC Serial Mode 56 07.96 ...
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Examples The interaction between ESCC2 and the CPU during transmission and reception of I-frames is illustrated in figure 26a, the flow control with RR/RNR during reception of I-frames in figure 26b, and during transmission of I-frames in figure 27a. Both, ...
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Half-Duplex SDLC-NRM Operation The LAP controllers of the two serial channels can be configured to function in a half-duplex Normal Response Mode (NRM), where they operate as a slave (secondary) station, by setting the NRM bit in the XBCH ...
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Reception of Frames The reception of frames functions similarly to the LAPB/LAPD operation (see chapter 5.2.1). Transmission of Frames The ESCC2 does not transmit S-, or I-frames if not instructed the primary station via an S-, ...
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Examples A few examples of ESCC2/CPU interaction in the case of NRM mode are shown in figure 28a to figure 29b. Figure 28a No Data to Send Figure 29a Data Transmission (no error) Semiconductor Group SAB 82532/SAF 82532 HDLC/SDLC Serial ...
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Error Handling Depending on the error type, erroneous frames are handled according to table 3. Table 3 Error Handling Frame Type Error Type I CRC error aborted unexpec. N(S) unexpec. N(R) S CRC error aborted unexpec. N(R) with I-field ...
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Figure 30 SDLC Loop The loop is formed by connecting TxD output of one station to the RxD input of the next one (refer to figure 30). This configuration is physically a loop, but logically a point-to-multipoint configuration. In every ...
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Figure 31 shows the state diagram for the Secondary. Note that in order to be able to hold ‘Active On Loop’ state ‘flags’ has to be selected as interframe time fill, as opposed to ‘idle’. Note: The Primary Station has ...
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Special Functions 5.4.1 Shared Flags The closing flag of a previously transmitted frame simultaneously becomes the opening flag of the following frame if there is one to be transmitted. The ‘Shared Flag’ feature is enabled by setting bit SFLG ...
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This feature can be profitably used e.g. for: • user specific protocol variations • line state monitoring, or • test purposes, in particular for monitoring or intentionally generating HDLC protocol rule violations (e.g. wrong CRC) Character or octet boundary synchronization ...
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Receive Length Check Feature The ESCC2 offers the possibility to supervise the maximum length of received frames and to terminate data reception in case this length is exceeded. This feature is controlled via the special Receive Length Check Register ...
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CRC ON/OFF Feature (version 2 upward option in non-auto mode or transparent mode 0, the internal handling of received and transmitted CRC checksum can be influenced via control bits CCR3:RCRC and CCR3:XCRC. Receive direction: The received CRC ...
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Asynchronous Serial Mode 6.1 Character Frame Character framing is achieved by special start and stop bits. Each data character is preceded by one Start bit and terminated by one or two stop bits. The character length is selectable from ...
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Data Reception 6.2.1 Operating Modes The ESCC2 offers the flexibility to combine clock modes, data encoding and data sampling in many different ways. However, only definite combinations make sense and are recommended for correct operation: Asynchronous Mode Prerequisites: • ...
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Storage of Data If the receiver is enabled, received data is stored in RFIFO (the LSB is received first). Moreover, the CD input may be used to control data reception. Character length, number of stop bits and the optional ...
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Flow Control by XON/XOFF (version 2 upward) Programmable XON and XOFF Two eight-bit control registers (XON, XOFF) contain the programmable values for XON and XOFF characters. The number of significant bits in a register is determined by the programmed ...
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Transmitter Status Bit The status bit ‘Flow Control Status’ (STAR:FCS) indicates the current state of the transmitter, as follows the transmitter is in XON state the transmitter is in XOFF state. Note: The transmitter cannot be ...
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Receiver For some applications it is desirable to provide means of out-of-band flow control to indicate to the far end transmitter that the local receiver’s buffer is getting full. This flow control can be used between two DTEs as shown ...
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Figure 34 shows an ESCC2 as a DTE connected to a DCE (MODEM equipment). The RTS feeds the RTS A bi-directional flow control. So when the DTE signal goes active HIGH which is sensed by the DCE and it stops ...
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In-band Flow Control Transparency In ASYNC modes an optional in-band flow control is provided with the XON/XOFF characters. If MODE:FLON bit = ‘1’ then the transmitter output is controlled based on recognition of the XON/XOFF characters at the receiver. ...
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Character Oriented Serial Mode (MONOSYNC/BISYNC) 7.1 Data Frame Character oriented protocols achieve synchronization between transmitting and receiving station by means of special SYN characters. Two examples are the MONOSYNC and IBM’s BISYNC procedures. BISYNC has two starting SYN characters ...
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Data Reception The receiver is generally activated by setting the RAC bit in the MODE register. Additionally, the CD signal may be used to control data reception. After issuing the HUNT command, the receiver monitors the incoming data stream ...
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Data Transmission Transmission of data written to XFIFO is initiated after the Transmit Frame command (XF) is issued (the LSB is sent out first). Additionally, the CTS signal may be used to control data transmission. Further data is requested ...
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Special Functions 7.4.1 Preamble Transmission If enabled via register CCR3, a programmable 8-bit pattern (register PRE) is transmitted with a selectable number of repetitions after Interframe Timefill transmission is stopped and a new frame is ready to be sent ...
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Serial Interface (layer-1 functions) The two serial interfaces of the ESCC2 provide two fully independent communication channels, supporting layer-1 functions to a high degree by various means of clock generation and clock recovery. Note: Since the two serial channels ...
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The transmit clock pins (TxCLK) may also output clock signals in certain clock modes if enabled via CCR2:TOE. The clocking source for the DPLL’s is always the internal BRG; the scaling factor (divider) of the BRG can be programmed through ...
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Clock Mode 1 (receive/transmit strobes) Externally generated, but identical receive and transmit clocks are supplied via RxCLK. In addition, a receive strobe can be connected via CD and a transmit strobe via TxCLK. These strobe signals work on a per ...
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CCR2 register, there are 9 bits to determine the location of a time-slot. Depending to the value programmed via those bits, the receive/transmit window (time-slot) starts with a delay of 1 (minimum delay 512 ...
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Clock Mode 6 (OSC – receive clock from DPLL) This clock mode is identical to clock mode 2 except that the clock for the BRG is delivered by the OSC and must not be supplied externally. Clock Mode 7 (OSC ...
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Note 2: Restrictions for frequency ratios between receive frequency ( f frequency ( ) and master clock frequency ( x Normal mode; clock mode 0, 2a, and 6a: Master clock mode: There are no restrictions on the relative phases of ...
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Figure 37 Short Low Phase of Transmit Clock for a Minimum of 2.5 Master Clock Cycles Figure 38 Long Low Phase of Transmit Clock for a Minimum of 2.5 Master Clock Cycles Note 4: If one of the clock modes ...
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Selectable Enhanced Resolution Baud Rate Generator (V3.x) Two features are provided to allow the ESCC2 to work with higher XTAL rates and support higher transmission baud rates. The first is XTAL clock divide-by-4 logic and the second is the enhanced ...
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Clock Recovery (DPLL) The ESCC2 offers the advantage of recovering the received clock from the received data by means of internal DPLL circuitry, thus eliminating the need to transfer additional clock information via the serial link. For this purpose, ...
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Now, the DPLL is more insensitive to high jitter amplitudes but needs more time to reach the optimal sampling position. To ensure correct data sampling preambles should precede the data information. Figures 39a, 39b and 40 explain the DPLL algorithms ...
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Figure 40 DPLL Algorithm for FM0, FM1 and Manchester Coding To supervise correct function when using bi-phase encoding, a status flag and a maskable interrupt inform about synchronous/asynchronous state of the DPLL. Semiconductor Group SAB 82532/SAF 82532 Serial Interface (layer-1 ...
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Bus Configuration Beside the point-to-point point-to-multipoint (pt-mpt, or bus) configurations by means of internal idle and collision detection/collision resolution methods pt-mpt configuration, comprising a central station (master) and several peripheral stations (slaves multimaster configuration ...
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Collisions During the transmission, the data transmitted on TxD is compared with the data on CxD. In case of a mismatch (‘1’ sent and ‘0’ detected, or vice versa) data transmission is immediately aborted, and idle (logical ‘1’) is ...
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When ten consecutive ‘1’s have been detected, transmission is allowed again and the priority class is increased (to eight ‘1’s). Inside a priority class, the order of transmission (individual priority) is based on the HDLC ...
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Data Encoding The ESCC2 supports the following coding schemes for serial data: – Non-Return-To-Zero (NRZ) – Non-Return-To-Zero-Inverted (NRZI) – FM0 (also known as Bi-Phase Space) – FM1 (also known as Bi-Phase Mark) – Manchester (also known as Bi-Phase) NRZ: ...
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FM0: An edge occurs at the beginning of every bit cell. A logical ‘0’ has an additional edge in the center of the bit cell, a logical ‘1’ has none. The transmit clock precedes the receive clock ...
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Manchester: In the first half of the bit cell the physical signal level corresponds to the logical value of the data bit. At the center of the bit cell this level is inverted. The transmit clock precedes the receive clock ...
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Modem Control Functions (RTS/CTS, CD) 8.5.1 RTS/CTS Handshaking The ESCC2 provides two pins (RTS, CTS) per serial channel supporting the standard RTS modem handshaking procedure for transmission control. A transmit request will be indicated by outputting logical ‘0’ on ...
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Figure 45 RTS-CTS Handshaking Beyond this standard RTS function, signifying a transmission request of a frame (Request To Send), the RTS output may be programmed for a special function via SOC1, SOC0 bits in the CCR2 register, provided the serial ...
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Test Mode To provide for fast and efficient testing, the ESCC2 can be operated in a test mode by setting the TLP bit in the MODE register. The on-chip serial input and output (TxD-RxD) are connected, generating a local ...
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Operational Description 9.1 Reset The ESCC2 is forced into the reset state if the RES pin is set ‘high’ for at least 5 microseconds. During RESET, the ESCC2 is temporarily in the power-up mode, and a subset of the ...
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Register Reset Value IMR0 FF H IMR1 FF H PIM FF H IPC 00 H PCR FF H IVA 00 H PRE 00 H XBCH 00 H STAR 48 H AML/MXN 00 H AMH/MXF 00 H TSAX 00 H TSAR ...
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Initialization After Reset the CPU has to write a minimum set of registers and an optional set dependent on the required features and operating modes. First, the serial mode, the configuration of the serial port and the clock mode ...
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Table 6 Initialization of ESCC2 (cont’d) Item Serial Mode Specific Features HDLC/SDLC ASYNC BISYNC User Demands Modem control lines Parallel port Semiconductor Group Registers MODE, TIMR XAD1, XAD2 RAH1, RAH2 RAL1, RAL2 XBCH CCR1 CCR2 CCR3 CCR4 PRE RLCR CCR1 ...
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Table 6 Initialization of ESCC2 (cont’d) Item Interrupt features DMA features Timer (external mode) Table 7 HDLC Specific Register Setup Address Mode Operating Mode Auto Non Auto Transparent Semiconductor Group Registers IPC IVA IMR0, IMR1 PIM XBCH CCR2 MODE, TIMR ...
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Operational Phase After having performed the initialization, the CPU switches each individual channel of the ESCC2 into operational phase by setting the PU bit in the CCR0 register. Initially, the CPU should bring the transmitter and receiver into a ...
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ASYNC: The transmission of character(s) can be started by issuing a XF command via the CMDR register. The ESCC2 will repeatedly request for the next data block by means of a XPR interrupt as soon as no more than 32 ...
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The activities at both serial and CPU interface during frame transmission (supposed frame length = 70 bytes) are shown in figure 47. Figure 47 Interrupt Driven Transmission Sequence Example (HDLC) Semiconductor Group SAB 82532/SAF 82532 Operational Description 107 07.96 ...
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DMA Mode Prior to data transmission, the length of the next frame (or the next block of characters transmitted must be programmed via the Transmit Byte Count Registers (XBCH, XBCL). The resulting byte count equals the programmed ...
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Data Reception 9.3.2.1 Interrupt Mode Also 2 32 byte FIFO buffers (receive pools) are provided for each channel in receive direction. There are different interrupt indications concerned with the reception of data: HDLC/SDLC • RPF (Receive Pool Full) interrupt, ...
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In addition to every received character the assigned status information Parity bit (0/1), Parity Error (yes/no), Framing Error (yes/no, ASYNC only!) is optionally stored in RFIFO. In addition to the end conditions (TCD interrupt or after RFRD command) the length ...
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DMA Mode If the RFIFO contains 32 bytes, the ESCC2 autonomously requests a block data transfer by DMA by activating the DRR line for as long as the start of the (word access) read cycle. This ...
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Detailed Register Description 10.1 Status/Control Registers in HDLC Mode 10.1.1 Register Addresses Address Register (A0 … A6) Channel A B Read Write 00 40 RFIFO XFIFO . . . . . . . . . . . . 1F ...
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Register Addresses (cont’d) Address Register (A0 … A6) Channel A B Read Write 2C 6C CCR0 2D 6D CCR1 2E 6E CCR2 2F 6F CCR3 30 70 – TSAX 31 71 – TSAR 32 72 – XCCR 33 73 ...
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Register Definitions Receive FIFO (RFIFO) Access: read Reading data from the RFIFO can be done in 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. The LSB is received first from the serial interface. In ...
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Transmit FIFO (XFIFO) Access: write Writing data to the XFIFO can be done in 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. The LSB is transmitted first. • Interrupt Mode Selected if DMA bit in ...
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XRNR … Transmit RNR (significant in auto-mode only!) Indicates the status of the ESCC2. 0 … receiver ready 1 … receiver not ready RRNR … Received RNR (significant in auto-mode only!) Indicates the status of the remote station. 0 … ...
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Command Register (CMDR) Access: write Value after RESET CMDR RMC RMC … Receive Message Complete Confirmation from CPU to ESCC2 that the current frame or data block has been fetched following an RPF or RME interrupt, thus ...
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XTF … Transmit Transparent Frame • Interrupt Mode • DMA Mode XIF … Transmit I-Frame (used in auto-mode only!) Initiates the transmission of an I-frame in auto-mode. Additionally to the opening flag sequence, the address and control field of the ...
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Preamble Register (PRE) Access: write Value after RESET PRE PR7 This register defines the pattern which is sent out during preamble transmission (refer to register CCR3). Note: It should be taken into consideration that Zero Bit Insertion ...
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Receive Status Register (RSTA) Access: read 7 RSTA VFR Note: The contents of the RSTA register relates to the last received HDLC frame and is updated when end-of-frame is recognized at the serial receive interface. Additionally, RSTA byte is copied ...
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CRC … CRC Compare/Check 0 … CRC check failed; received frame contains errors. 1 … CRC check o.k.; received frame is error-free. RAB … Receive Message Aborted The received frame was aborted from the transmitting station. According to the HDLC ...
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Mode Register (MODE) Access: read/write Value after RESET MODE MDS1 MDS1 … MDS0 … Mode Select The operating mode of the HDLC controller is selected. 00 … auto-mode 01 … non auto-mode 10 … transparent mode 11 ...
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TMD … Timer Mode Determines the operating mode of the timer. 0 … external mode 1 … internal mode RAC … Receiver Active Switches the receiver to operational or inoperational state. 0 … receiver inactive 1 … receiver active In ...
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Timer Register (TIMR) Access: read/write 7 TIMR VALUE … (5 bits) Sets the time period where – the timer resolution factor which is either 32 768 or 512 – TCP is the clock period ...
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Version 3.x TIMR Timer Register (READ/WRITE) is unchanged. However the input to the timer function can be optionally selected to be XTAL/4 in master clock mode by setting CCR0:MCE = ‘1’ and CCR4:MCK4 = ‘1’. VALUE … (5 bits) sets ...
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Transmit Address Byte 1 (XAD1) Access: read/write 7 2-byte address XAD1 7 1-byte address XAD1 XAD1 (and XAD2) can be programmed with one individual address byte which is appended automatically to the frame by ESCC2 in auto-mode. The function depends ...
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Transmit Address Byte 2 (XAD2) Access: read/write 7 2-byte address XAD2 7 1-byte address XAD2 Second individually programmable address byte. – 2-byte address (MODE:ADM = ‘1’) XAD2 constitutes the low byte of the 2 byte address field (In ISDN LAPD, ...
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Receive Address Byte High Register 1 (RAH1) Access: write 7 RAH1 In operating modes that provide high byte address recognition, the high byte of the received address is compared with the individually programmable values in RAH1 and RAH2. In version ...
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Receive Address Byte High Register 2 (RAH2) Access: write 7 RAH2 RAH2 … Value of second individual high address byte. MCS … Modulo Count Select (valid in auto-mode only!) The MCS bit determines the HDLC control field format. 0 … ...
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Receive Address Byte Low Register 1 (RAL1) Access: read/write 7 RAL1 The general function (WRITE or READ) and the meaning or contents of this register depend on the selected operating mode: • Auto- / Non-Auto-Mode (16-bit address) – WRITE Access ...
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Receive HDLC Control Register (RHCR) Access: read 7 RHCR Value of the HDLC control field of the last received frame. Note: RHCR is copied into RFIFO for every frame. Receive Address Byte Low Register 2 (RAL2) Access: write 7 RAL2 ...
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Transmit Byte Count Low (XBCL) Access: write 7 XBCL XBC7 Together with XBCH (bits XBC11 … XBC8) this register is used in DMA mode only, to program the length (1 … 4096 bytes) of the next frame to be transmitted. ...
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Transmit Byte Count High (XBCH) Access: write Value after RESET: 000xxxxx 7 XBCH DMA DMA … DMA Mode Selects the data transfer mode of ESCC2 to/from System Memory. 0 … Interrupt controlled data transfer (Interrupt Mode). 1 … DMA controlled ...
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Channel Configuration Register 0 (CCR0) Access: read/write Value after RESET CCR0 PU Note: Unused bits have to be set to logical ‘0'. PU … Switches between power-up and power-down mode 0 … power-down (standby) 1 … power-up ...
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Channel Configuration Register 1 (CCR1) Access: read/write Value after RESET CCR1 SFLG SFLG … Enable Shared Flags If this bit is set, the closing FLAG of a preceding frame simultaneously becomes the opening FLAG of the following ...
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ODS … Output Driver Select Defines the function of the transmit data pin (TxD) 0 … TxD pin is an open drain output. 1 … TxD pin is a push-pull output. Note: This feature is also valid for pin RxD ...
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Channel Configuration Register 2 (CCR2) Access: read/write Value after RESET The meaning of the individual bits in CCR2 depends on the clock mode selected via CCR1 as follows: CCR2 7 SOC1 clock mode 0a, 1 clock mode 0b, ...
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BDF … Baud Rate Division Factor 0 … The division factor of the baud rate generator is set to ‘1’ 1 … The division factor is determined by BR9 … BR0 bits in SSEL … Clock Source Select Selects the ...
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Channel Configuration Register 3 (CCR3) Access: read/write Value after RESET CCR3 PRE1 PRE1 … PRE0 … Number of Preamble Repetition If preamble transmission is initiated, the preamble defined via register PRE is transmitted 00 … 1 times ...
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RCRC … Receive CRC ON/OFF Only applicable in non-auto mode and transparent mode 0. If this bit is set to ‘1’, the received CRC checksum will be written to RFIFO (CRC-CCITT: 2 bytes; CRC-32: 4 bytes). The checksum, consisting of ...
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Time-Slot Assignment Register Transmit (TSAX) Access: write Value after RESET Note: This register is only used in clock mode 5! 7 TSAX TSNX … Time-Slot Number Transmit Selects one possible time-slots (00 data is ...
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Transmit Channel Capacity Register (XCCR) Access: write Value after RESET Note: This register is only used in clock mode 5! 7 XCCR XBC7 XBC7 … XBC0 … Transmit Bit Number Count, Bit 7 … 0 Defines the number ...
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Version Status Register (VSTR) Access: read 7 VSTR CD CD … Carrier Detect This bit reflects the state of the CD pin. 1 … CD active 0 … CD inactive DPLA … DPLL Asynchronous This bit is only valid when ...
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Baud Rate Generator Register (BGR) Access: write 7 BGR BR7 BR7 … BR0 … Baud Rate, bits 7 … 0 The Baud Rate generator divisor consists of bits BR0-7 from BRG register and bits BR8-9 from the CCR2 register. The ...
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Receive Length Check Register (RLCR) Access: write 7 RLCR RC RC … Receive Check (on/off) 0 … Receive Length Check feature disabled 1 … Receive Length Check feature enabled RL6 … RL0 … Receive Length The maximum receive length after ...
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Address Mask High (AMH) (version 2 upwards) Access: write Value after RESET AMH AMH7 The function is similar to AML but with respect to register RAH1. Global Interrupt Status Register (GIS) Access: read Value after RESET: 00 ...
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Interrupt Vector Address (IVA) Access: write Value after RESET IVA T7 Note: Unused bits have to be set to logical ‘0’. IVA is accessible via both channel addresses (38 T7 … T3 … Interrupt Vector Address These ...
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Interrupt Port Configuration (IPC) Access: read/write Value after RESET IPC VIS Note: Unused bits have to be set to logical ‘0’. IPC is accessible via both channel addresses (39 VIS … Masked Interrupts Visible 0 … Masked ...
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Interrupt Status Register 0 (ISR0) Access: read Value after RESET ISR0 RME All bits are reset when ISR0 is read. Additionally, RME and RPF are reset when the corresponding interrupt vector is output. Note: If bit IPC:VIS ...
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PCE … Protocol Error (significant in auto-mode only) The ESCC2 has detected a protocol error, i.e. it has received – I-frame with incorrect N(R) – an S-frame containing an I-field. PLLA … DPLL Asynchronous This bit is ...
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Interrupt Status Register 1 (ISR1) Access: read Value after RESET ISR1 EOP All bits are reset when ISR1 is read. Additionally, XPR is reset when the corresponding interrupt vector is output. Note: If bit IPC:VIS is set ...
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AOLP/ALLS … Active On Loop Only valid if SDLC Loop mode is selected set in response Active On Loop command, but not before an EOP sequence has been received. TxD is disconnected from RxD and ...
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CSC … Clear To Send Status Change Indicates that a state transition has occurred on CTS. The actual state can be read from STAR register (CTS bit). XMR … Transmit Message Repeat The transmission of the last frame has to ...
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Interrupt Mask Register 0, 1 (IMR0,1) Access: write Value after RESET IMR0 RME MR1 EOP Each interrupt source can generate an interrupt signal at port INT (function of the output stage is defined via register ...
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Port Interrupt Status Register (PIS) Access: read 7 PIS PIS7 Each of the above bits is assigned to the Universal Port pin (P0 … P7) with the same number. Bit PISn is set and an interrupt is generated on INT ...
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Port Interrupt Mask Register (PIM) Access: write Value after RESET PIM PIM7 Each of the above bits is assigned to the Universal Port pin (P0 … P7) and to the bits of register PIS with the same ...
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Channel Configuration Register 4 (CCR4) (version 2 upwards, otherwise unused) Access: read/write Value after RESET CCR4 MCK4 EBRG Note: Unused bits have to be set to ‘0’. MCK4 … Master Clock divide-by-4 (V3 upwards, otherwise unused) This ...
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RFT, RFT0 ... RFIFO Threshold Level The size of the accessible part of RFIFO can be determined by programming these bits. The number of valid bytes after an RPF interrupt is given in the following table: RFT1 ...
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Status/Control Registers in ASYNC Mode 10.2.1 Register Addresses Address Register (A0 … A6) Channel A B Read Write 00 40 RFIFO XFIFO Receive/Transmit FIFO . . . . . . STAR CMDR Status Register/Command Register ...
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Register Addresses (cont’d) Address Register (A0 … A6) Channel A B Read Write 30 70 – TSAX Time-slot Assignment Register Transmit 31 71 – TSAR Time-slot Assignment Register Receive 32 72 – XCCR Transmit Channel Capacity Register 33 73 ...
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Register Definitions Receive FIFO (RFIFO) Access: read Received data stored in RFIFO (LSB is received first) can be organized in one of two selectable ways (refer to figure 51): – pure data character length of 8 ...
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Interrupt Controlled Data Transfer (interrupt mode) Selected if DMA bit in XBCH is reset bytes/16 words of received data can be read from the RFIFO following a RPF or a TCD interrupt depending on the selected RFIFO ...
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Transmit FIFO (XFIFO) Access: write Writing data to XFIFO can be in 8-bit (byte) or 16-bit (word) access depending on the selected bus interface mode. The LSB is transmitted first. Interrupt Mode Selected if DMA bit in XBCH is reset. ...
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Status Register (STAR) Access: read Value after RESET STAR XDOV XDOV … Transmit Data Overflow More than 32 bytes have been written to the XFIFO. This bit is reset by: – a transmitter reset command XRES – ...
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TEC … TIC Executing This status bit indicates that transmission instruction of currently programmed TIC (Transmit Immediate Character) is accepted but not completely executed. Further access to register TIC is only allowed after STAR:TEC has been reset by the ESCC2. ...
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Command Register (CMDR) Access: write Value after RESET CMDR RMC Note: Unused bits have to be set to logical ‘0’. RMC … Receive Message Complete Confirmation from CPU to ESCC2 that the current frame or data block ...
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XF … Transmit Frame • Interrupt Mode After having written bytes/16 words to the XFIFO, this command initiates the transmission of data. • DMA Mode After having written the amount of data to be transmitted to the ...
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Mode Register (MODE) Access: read/write Value after RESET MODE 0 Note: Unused bits have to be set to logical ‘0’. FRTS … Flow Control Using RTS (V3.x, otherwise unused) This bit is used in combination with the ...
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FLON … Flow Control ON The in-band flow control is activated via this bit: 0 … No further action is automatically taken by the ESCC2. 1 … The reception of an XOFF character (defined via register RAC … Receiver Active ...
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Timer Register (TIMR) Access: read/write 7 TIMR VALUE … (5 bits) Sets the time period where – the timer resolution factor which is either 32 768 or 512 – TCP is the clock period ...
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Version 3.x: TIMR Timer Register (READ/WRITE) is unchanged. However the input to the Timer function can be optionally selected to be XTAL/4 in Master clock mode by setting CCR0:MCE = ‘1’ and CCR4:MCK4 = ‘1’. VALUE … (5 bits) sets ...
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XON Character (XON) Access: read/write Value after RESET XON XON7 This register is used to specify the XON character. It can be used in conjunction with the interrupt status ISR1:XON for automatic in-band flow control (if MODE:FLON ...
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Termination Character Register (TCR) Access: read/write Value after RESET TCR TCR7 TCR7 … TCR0 … Termination Character If enabled via register RFC the received data stream is monitored for the occurrence of a programmed ‘termination character’. When ...
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STOP … Stop Bit This bit defines the number of stop bits generated by the transmitter: 0 … 1 stop bit 1 … 2 stop bits. PAR1, PAR0 … Parity Format If parity check/generation is enabled by setting PARE, these ...
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RFIFO Control Register (RFC) Access: read/write Value after RESET RFC 0 Note: Unused bits have to be set to logical ‘0’. DPS … Disable Parity Storage Only valid if parity check/generation is enabled via DAFO:PARE and character ...
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RFDF = ‘0’ • character 5 … 8 bit or • character 5 … 7(8) 1) Parity bit is lost. Data Byte FE: framing error (P): can be disabled via bit DPS RFTH1, RFTH0 … RFIFO Threshold Level These bits ...
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Receive Byte Count Low (RBCL) Access: read 7 RBCL RBC7 Indicates the number of valid bytes available in the accessible part of the RFIFO. This register must be read by the CPU following a TCD interrupt. In case of a ...
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Received Byte Count High (RBCH) Access: read Value after RESET: 000xxxxx 7 RBCH DMA DMA, CAS … These bits represent the read-back value programmed in XBCH RBC11 … RBC8 … Receive Byte Count (most significant bits) No function in ASYNC ...
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Transmit Byte Count High (XBCH) Access: write Value after RESET: 000xxxxx 7 XBCH DMA Note: Unused bits have to be set to logical ‘0’. DMA … DMA Mode Selects the data transfer mode of ESCC2 to/from System Memory. 0 … ...
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Channel Configuration Register 0 (CCR0) Access: read/write Value after RESET CCR0 PU Note: Unused bits have to be set to logical ‘0’. PU … Switches between Power-up and Power-down Mode 0 … power-down (standby) 1 … power-up ...
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Channel Configuration Register 1 (CCR1) Access: read/write Value after RESET CCR1 0 Note: Unused bits have to be set to logical ‘0’. ODS … Output Driver Select Defines the function of the transmit data pins (T DA, ...
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Channel Configuration Register 2 (CCR2) Access: read/write Value after RESET The meaning of the individual bits in CCR2 depends on the clock mode selected via CCR1 as follows: CCR2 7 SOC1 clock mode 0a, 1 clock mode 0b, ...
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BDF … Baud Rate Division Factor 0 … The division factor of the baud rate generator is set 1 … The division factor is determined by BR9 … BR0 bits in SSEL … Clock Source Select Selects the clock source ...
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Channel Configuration Register 3 (CCR3) (Version 2 upwards) Access: read/write Value after RESET CCR3 0 Note: Unused bits have to be set to logical ‘0’. PSD … DPLL Phase Shift Disable Only applicable in the case of ...
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Time-Slot Assignment Register Receive (TSAR) Access: write Value after RESET Note: This register is only used in clock mode 5! 7 TSAR TSNR … Time-slot Number Receive Defines one possible time-slots (00 data is ...
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Receive Channel Capacity Register (RCCR) Access: write Value after RESET Note: This register is only used in clock mode 5! 7 RCCR RBC7 RBC7 … RBC0 ... Receive Bit Number Count, Bit 7 … 0 Defines the number ...
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Baud Rate Generator Register (BGR) Access: write 7 BGR BR7 BR7 … BR0 … Baud Rate, bits 7 … 0 The Baud Rate generator divisor consist of bits BR0-7 from BRG register and bits BR8-9 from the CCR2 register. The ...
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Transmit Immediate Character (TIC) (Version 2 upwards) Access: write 7 TIC TIC7 When a character is written into this register its contents are inserted in the outgoing character stream – immediately upon writing this register by the microprocessor if the ...
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Mask XON Character (MXN) (Version 2 upwards) Access: write Value after RESET MXN MXN7 This register is used to masked single bit positions of the XON character. Refer to the description of the XON register. The number ...
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Global Interrupt Status Register (GIS) Access: read Value after RESET GIS PI This status register points to pending – channel assigned interrupts: ISA0 ISR0, ISA1 ISB0 ISR0, ISB1 – universal port interrupts: PI PIS accessible ...
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Interrupt Port Configuration (IPC) Access: read/write Value after RESET IPC VIS Note: Unused bits have to be set to logical ‘0’. IPC is accessible via both channel addresses (39 VIS … Masked Interrupts Visible 0 … Masked ...
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Interrupt Status Register 0 (ISR0) Access: read Value after RESET ISR0 TCD All bits are reset when ISR0 is read. Additionally, TCD and RPF are reset when the corresponding interrupt vector is output. Note: If bit IPC:VIS ...
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PLLA… DPLL Asynchronous This bit is only valid when the receive clock is supplied by the DPLL and FM0, FM1 or Manchester data encoding is selected set when the DPLL has lost synchronization. Reception is disabled (IDLE is ...
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BRK … Break This bit is set when a break signal – static low level for a time equal to (character length + parity + stop bit(s)) – is detected on RxD. BRKT … Break Terminated This bit is set ...
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Interrupt Mask Register 0, 1 (IMR0, IMR1) Access: write , Value after RESET IMR0 TCD IMR1 1 Note: Unused bits have to be set to logical ‘1’. Each interrupt source can generate an interrupt signal at port ...
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Port Interrupt Status Register (PIS) Access: read 7 PIS PIS7 PIS is accessible via both channel addresses (3D Each of the above bits is assigned to the Universal Port pin (P0 … P7) with the same number. Bit PISn is ...
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Port Interrupt Mask Register (PIM) Access: write Value after RESET PIM PIM7 PIM is accessible via both channel addresses (3D Each of the above bits is assigned to the Universal Port pin (P0 … P7) and to ...
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Channel Configuration Register 4 (CCR4) (Version 3 upwards, otherwise unused) Access: read/write Value after RESET CCR4 MCK4 EBRG Note: Unused bits have to be set to logical ‘0’. MCK4 … Master Clock divide-by-4 This bit is valid ...
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Status/Control Registers in BISYNC Mode 10.3.1 Register Addresses Address Register (A0 … A6) Channel A B Read Write 00 40 RFIFO XFIFO Receive/Transmit FIFO . . . . . . STAR CMDR Status Register/Command Register ...
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Register Addresses (cont’d) Address Register (A0 … A6) Channel A B Read Write 30 70 – TSAX Time-slot Assignment Register Transmit 31 71 – TSAR Time-slot Assignment Register Receive 32 72 – XCCR Transmit Channel Capacity Register 33 73 ...