AD1848KP Analog Devices, AD1848KP Datasheet
AD1848KP
Specifications of AD1848KP
Available stocks
Related parts for AD1848KP
AD1848KP Summary of contents
Page 1
... R_AUX2 REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
Page 2
AD1848K–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 Digital Supply (V ) 5.0 DD Analog Supply (V ) 5.0 CC Word Rate ( Input Signal 1008 Analog Output Passband kHz ADC FFT ...
Page 3
DIGITAL DECIMATION AND INTERPOLATION FILTERS* Passband Passband Ripple Transition Band Stopband Stopband Rejection Group Delay Group Delay Variation Over Passband ANALOG-TO-DIGITAL CONVERTERS Resolution (No Missing Codes from 10 LSB Ramp Around Midscale)* Dynamic Range (–60 dB Input, THD+N Referenced to ...
Page 4
AD1848K DAC ATTENUATOR Step Size ( –34.5 dB) Step Size (– –94.5 dB)* Output Attenuation Range Span* ANALOG OUTPUT Full-Scale Output Voltage Output Impedance External Load Impedance Output Capacitance External Load Capacitance V REF V Current ...
Page 5
TIMING PARAMETERS (GUARANTEED OVER OPERATING TEMPERATURE RANGE AND V WR/RD Strobe Width (t ) STW WR/RD Rising to WR/RD Falling (t BWND Write Data Setup to WR Rising (t WDSU RD Falling to Valid Read Data (t ) RDDV CS ...
Page 6
... DD GNDD 16 17 XTAL1I AD1848K XTAL1O TOP VIEW GNDD 20 XTAL2I 21 XTAL2O 22 PWRDWN GNDD 26 R_FILT CONNECT Units Model V V AD1848KP AD1848KST 10.0 mA +85 C +150 C V 64-Lead Thin Quad Flatpack Pinout ADR0 CDAK 2 58 XCTL1 CDRQ 3 57 INT PDAK 4 56 XCTL0 PDRQ GNDD DD 7 ...
Page 7
PIN DESCRIPTION Parallel Interface Pin Name PLCC TQFP I/O CDRQ CDAK PDRQ PDAK ADR1:0 9 & & ...
Page 8
AD1848K Analog Signals Pin Name PLCC TQFP L_LINE 30 21 R_LINE 27 18 L_MIC 29 20 R_MIC 28 19 L_AUX1 39 30 R_AUX1 42 33 L_AUX2 38 29 R_AUX2 43 34 L_OUT 40 31 R_OUT 41 32 Miscellaneous Pin Name ...
Page 9
DAC output. The microphone inputs can pass through optional 20 dB gain blocks. A software-controlled pro- grammable gain stage allows independent gain for each channel going ...
Page 10
AD1848K Digital Mixing Stereo digital output from the ADCs can be mixed digitally with the input to the DACs. Digital output from the ADCs going out of the data port is unaffected by the digital mix. Along the digi- tal ...
Page 11
CONTROL REGISTERS Control Register Architecture The AD1848K SoundPort Stereo Codec accepts both data and control information through its byte-wide parallel port. Indirect addressing minimizes the number of external pins required to access all 21 of its byte-wide internal registers. Only ...
Page 12
AD1848K Direct Control Register Definitions Index Register (ADR1 ADR1:0 Data 7 Data 6 0 INIT MCE IXA3:0 Index Address. These bits define the address of the AD1848K register accessed by the Indexed Data Register. These bits are read/write. ...
Page 13
Status Register (ADR1 ADR1:0 Data 7 Data 6 2 CU/L CL/R INT Interrupt Status. This sticky bit (the only one) indicates the status of the interrupt logic of the AD1848K. This bit is cleared by any host write ...
Page 14
AD1848K PIO Data Registers (ADRI : ADR1:0 Data 7 Data 6 3 CD7 CD6 The PIO Data Registers are two registers mapped to the same address. Writes send data to the ...
Page 15
Right Input Control (IXA3 IXA3:0 Data 7 Data 6 1 RSS1 RSS0 RIG3:0 Right Input Gain Select. The least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB. res Reserved for future expansion. ...
Page 16
AD1848K Left Auxiliary #2 Input Control (IXA3 IXA3:0 Data 7 Data 6 4 LMX2 res LX2A4:0 Left Auxiliary Input #2 Attenuate Select. The least significant bit of this gain/attenuate select represents –1.5 dB. LX2A4 produces a ...
Page 17
Clock and Data Format Register (IXA3 IXA3:0 Data 7 Data 6 8 res FMT The contents of the Clock and Data Format Register cannot be changed except when the AD1848K is in Mode Change Enable (MCE) state. Write ...
Page 18
AD1848K Interface Configuration Register (IXA3 IXA3:0 Data 7 Data 6 9 CPIO PPIO The contents of the Interface Configuration Register cannot be changed except when the AD1848K is in Mode Change Enable (MCE) state. Write attempts to this ...
Page 19
Test and Initialization Register (IXA3:0 = 11) IXA3:0 Data 7 Data COR PUR ORL1:0 Overrange Left Detect. These bits indicate the overrange on the left input channel. This bit changes on a sample-by sample basis. This bit ...
Page 20
AD1848K Digital Mix Control Register (IXA3:0 = 13) IXA3:0 Data 7 Data DMA5 DMA4 DME Digital Mix Enable. This bit will enable the digital mix of the ADCs’ output with the DACs’ input. When enabled, the data ...
Page 21
DATA AND CONTROL TRANSFERS The AD1848K SoundPort Stereo Codec supports a DMA re- quest/grant architecture for transferring data with the host com- puter bus. One or two DMA channels can be supported. Programmed I/O (PIO) mode is also supported for ...
Page 22
AD1848K For read/capture cycles, the AD1848K will place data on the DATA7:0 lines while the host is asserting the read strobe, RD, by holding it LO. For write/playback, the host must place data on the DATA7:0 pins while strobing the ...
Page 23
ISA BUS BCLK CDRQ OUTPUT t DRHD t DKSU CDAK INPUT t DBDL DBEN & DBDIR OUTPUTS t STW RD INPUT t RDDV DATA7:0 OUTPUTS Figure 13. AD1848K 8-Bit Mono DMA Read/Capture Cycle ISA BUS BCLK CDRQ/ PDRQ OUTPUTS CDAK/ ...
Page 24
... Status Register’s INT bit may be set. POWER UP AND RESET The PWRDWN pin should be held in its active LO state when power is first applied to the AD1848K. Analog Devices recom- mends waiting one full second after deasserting PWRDWN be- fore commencing audio activity with the AD1848K. This will allow the analog outputs to fully settle to the V prior to system autocalibration ...
Page 25
... APPLICATIONS CIRCUITS The AD1848K Stereo Codec has been designed to require a minimum of external circuitry. The recommended circuits are shown in Figures 17 through 25. Analog Devices estimates that the total cost of all the components shown in these figures, in- cluding crystals but not including connectors less than $10 in the U ...
Page 26
... F Figure 24. AD1848K Recommended Power Supply Bypassing Analog Devices recommends a split ground plane as shown in Figure 25. The analog plane and the digital plane are connected directly under the AD1848K. Splitting the ground plane directly under the SoundPort Codec is optimal because analog pins will ...
Page 27
FREQUENCY RESPONSE PLOTS 10 0 –10 –20 –30 –40 –50 dB –60 –70 –80 –90 –100 –110 –120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 SAMPLE FREQUENCY (F Figure 26. AD1848K Analog-to-Digital Frequency Response (Full-Scale Line-Level Inputs Gain) ...
Page 28
AD1848K P-68A 68-Lead Plastic Leaded Chip Carrier 0.175 (4.45) 0.995 (25.27) 0.169 (4.29) SQ 0.885 (22.48 PIN 1 IDENTIFIER TOP VIEW 0.954 (24.23) SQ 0.104 (2.64) TYP 0.950 (24.13) INDEX PRODUCT OVERVIEW ...