AM28F010-90JC Advanced Micro Devices, AM28F010-90JC Datasheet

no-image

AM28F010-90JC

Manufacturer Part Number
AM28F010-90JC
Description
1 megabit CMOS 12.0 volt, bulk erase flash memory
Manufacturer
Advanced Micro Devices
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AM28F010-90JC
Manufacturer:
AMD
Quantity:
6 220
Part Number:
AM28F010-90JC
Manufacturer:
AMD
Quantity:
20 000
Am28F010
1 Megabit (128 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am28F010 is a 1 Megabit Flash memory orga-
nized as 128 Kbytes of 8 bits each. AMD’s Flash mem-
ories offer the most cost-effective and reliable read/
write non-volatile random access memor y. The
Am28F010 is packaged in 32-pin PDIP, PLCC, and
TSOP versions. It is designed to be reprogrammed
and erased in-system or in standard EPROM pro-
grammers. The Am28F010 is erased when shipped
from the factory.
The standard Am28F010 offers access times as fast as
70 ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the Am28F010 has separate chip enable (CE#) and
output enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
Am28F010 uses a command register to manage this
functionality, while maintaining a JEDEC Flash Stan-
dard 32-pin pinout. The command register allows for
100% TTL level control inputs and fixed power supply
levels during erase and programming, while maintain-
ing maximum EPROM compatibility.
Publication# 11559
Issue Date: January 1998
High performance
— 70 ns maximum access time
CMOS Low power consumption
— 30 mA maximum active current
— 100 µA maximum standby current
— No data retention power consumption
Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
10,000 write/erase cycles minimum
Write and erase voltage 12.0 V 5%
Latch-up protected to 100 mA
from –1 V to V
FINAL
Rev: H Amendment/+2
CC
+1 V
AMD’s Flash technology reliably stores memory con-
tents even after 10,000 erase and program cycles. The
AMD cell is designed to optimize the erase and pro-
gramming mechanisms. In addition, the combination of
advanced tunnel oxide processing and low internal
electric fields for erase and programming operations
produces reliable cycling. The Am28F010 uses a
12.0 V 5% V
Flasherase and Flashrite algorithms.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to V
The Am28F010 is byte programmable using 10 ms pro-
gramming pulses in accordance with AMD’s Flashrite
programming algorithm. The typical room temperature
programming time of the Am28F010 is two seconds.
The entire chip is bulk erased using 10 ms erase pulses
according to AMD’s Flasherase alrogithm. Typical era-
sure at room temperature is accomplished in less than
one second. The windowed package and the 15–20
Flasherase™ Electrical Bulk Chip-Erase
— One second typical chip-erase
Flashrite™ Programming
— 10 µs typical byte-program
— Two seconds typical chip program
Command register architecture for
microprocessor/microcontroller compatible
write interface
On-chip address and data latches
Advanced CMOS flash memory technology
— Low cost single transistor memory cell
Automatic write/erase pulse stop timer
PP
high voltage input to perform the
CC
+1 V.

Related parts for AM28F010-90JC

AM28F010-90JC Summary of contents

Page 1

... AMD’s proprietary non-epi process. Latch-up pro- tection is provided for stresses up to 100 milliamps on address and data pins from – The Am28F010 is byte programmable using 10 ms pro- gramming pulses in accordance with AMD’s Flashrite programming algorithm. The typical room temperature programming time of the Am28F010 is two seconds ...

Page 2

... During write cycles, the command register internally latches address and data needed for the programming and erase operations. For system design simplifica- tion, the Am28F010 is designed to support either WE# or CE# controlled writes. During a system write cycle, addresses are latched on the falling edge of WE# or CE# whichever occurs last ...

Page 3

... A15 3 30 A12 DQ0 DQ1 14 DQ2 Note: Pin 1 is marked for orientation WE# (W#) NC A14 A13 A11 A2 10 OE# (G A10 A0 12 CE# (E#) DQ0 13 DQ7 DQ6 DQ5 DQ4 DQ3 11559H-2 Am28F010 PLCC A14 29 A13 A11 25 24 OE# (G#) A10 23 CE# (E#) 22 DQ7 11559H-3 3 ...

Page 4

... CONNECTION DIAGRAMS (continued) 1 A11 A13 5 A14 A16 11 A15 A12 A10 LOGIC SYMBOL 4 TSOP 32-Pin TSOP—Standard Pinout 32-Pin TSOP—Reverse Pinout 17 A0–A16 DQ0–DQ7 CE # (E#) OE# (G#) WE# (W#) Am28F010 A10 # A11 A13 28 A14 A16 22 A15 21 A12 11559H-4 8 11559H-5 ...

Page 5

... AM28F010 -70 J DEVICE NUMBER/DESCRIPTION Am28F010 1 Megabit (128 K x 8-Bit) CMOS Flash Memory Valid Combinations AM28F010-70 AM28F010-90 AM28F010-120 AM28F010-150 AM28F010-200 C B OPTIONAL PROCESSING Blank = Standard Processing B = Burn-In Contact an AMD representative for more information. TEMPERATURE RANGE C = Commercial (0°C to +70° Industrial (–40°C to +85° Extended (– ...

Page 6

... The tar- get address is latched on the falling edge of the Write Enable pulse and the appropriate data is latched on the rising edge of the pulse. Write Enable high inhibits writing to the device. Am28F010 5% or 10%) must be at high voltage in ...

Page 7

... The device also incorporates several features to pre- vent inadvertent write cycles resulting from V up and power-down transitions or system noise. Low V Write Inhibit CC To avoid initiation of a write cycle during V and power-down, the device locks out write cycles for Am28F010 power- CC power- ...

Page 8

... V. See DC Characteristics for voltage levels IL IH PPL 2 memory contents can be read but not written or erased. PP PPL (standby and V should not exceed 10.0 volts. Also, the Am28F010 has Am28F010 . To initiate a write cycle CE# and IH will not accept commands on the rising (Note PPL V X ...

Page 9

... V code. For the device these two bytes are given in Table 2 below. All identifiers for manufacturer and device codes will exhibit odd parity with the MSB (DQ7) de- fined as the parity bit. Table 2. Am28F010 Auto Select Code Am28F010 (11 13 address A9. Two ID from ...

Page 10

... In order to write, OE# must and CE# and WE# IH must any pin is not in the correct state a write IL command will not be executed. Table 3. Am28F010 Command Definitions Operation Command (Note 4) Read Memory Read Auto select Erase Setup/Erase Write Erase-Verify Program Setup/Program ...

Page 11

... Program Setup) to the command register. Figure 1 and Table 4, the Flasherase electrical erase algorithm, illustrate how commands and bus operations are combined to per- form electrical erasure. Refer to AC Erase Characteris- tics and Waveforms for specific timing parameters. Am28F010 11 ...

Page 12

... Data = FFh, reset the register for read operations Wait for V PP parameters. The V power supply can be hard-wired to the device may be ground, no connect with a resistor tied to ground, or less than V PPL Am28F010 pin. Figure 1 illustrates the electrical PP Comments Ramp to V (Note 1) PPH ) WHWH2 ...

Page 13

... Read Data from Device No Increment PLSCNT = PLSCNT 1000 Yes Apply V PPL Erase Error Write Reset Command Figure 1. Flasherase Electrical Erase Algorithm Am28F010 Start Data = 00h No Apply V PPH Address = 00h PLSCNT = 0 Time out 10 ms Write Erase Verify Time out 6 µs No Data = FFh ...

Page 14

... This command terminates the erase oper- ation on the rising edge of the WE# pulse (section D). The Erase-verify command also stages the device for data verification (section F). After each erase operation each byte must be verified. The byte address to be verified must be supplied with Am28F010 Data Out ...

Page 15

... Most bytes verify after the first or second pulse. The entire sequence of pro- gramming and byte verification is performed with high voltage applied to the V PP lustrate the programming algorithm. Am28F010 pin. Figure 3 and Table 5 il- 15 ...

Page 16

... Write Program Command (A/D) Time out 10 µs Write Program Verify Command Time out 6 µs Read Data from Device No Verify Byte Increment PLSCNT Yes No Last Address Yes Write Reset Command Apply V PPL Programming Completed Flashrite Programming Algorithm Am28F010 No PLSCNT = 25? Yes Apply V PPL Device Failed 11559G-8 ...

Page 17

... Compare Data Output to Data Expected Data = FFh, resets the register for read operations. Wait for V PP parameters. The V power supply can be hard-wired to the device may be ground, no connect with a resistor tied to ground, or less than V PPL Am28F010 Comments Ramp to V (Note 1) PPH ) WHWH1 Ramp to V (Note 1) PPL + 2 ...

Page 18

... Upon completion of the program timing routine, the mi- croprocessor must write the program-verify command (C0h). This command terminates the programming op- eration on the rising edge of the WE# pulse (section D). The program-verify command also stages the device for data verification (section F). Another software timing Am28F010 Data Out ...

Page 19

... Programming In-System Flash memories can be programmed in-system standard PROM programmer. The device may be sol- dered to the circuit board upon receipt of shipment and programmed in-system. Alternatively, the device may initially be programmed in a PROM programmer prior to soldering the device to the board. Am28F010 CC and ...

Page 20

... The operation is initiated by writing 80h or 90h into the command register. Following this command, a read cycle address 0000h retrieves the manufacturer code of 01h. A read cycle from address 0001h returns the device code. To terminate the operation necessary to write another valid command, such as Reset (FFh), into the register. Am28F010 ...

Page 21

... Read . . . . . . . . . . . . . . . . . . . . . . . . –0 +12.6 V Program, Erase, and Verify . . . . . . +11 +12 –2.0 V for SS Operating ranges define those limits between which the functionality of the device is guaranteed. + 2.0V for periods up pins is -0 may overshoot PP Am28F010 ). . . . . . . . . . . .0°C to +70° .–40°C to +85° .–55°C to +125° ...

Page 22

... MAXIMUM OVERSHOOT +0.8 V –0.5 V – 2.0 V 14 Maximum Negative Input Overshoot Maximum Positive Input Overshoot Maximum V Overshoot PP Am28F010 11559H-10 11559H-11 11559H-12 ...

Page 23

... Read/Write PP V PPH Operations V Low V Lock-out Voltage LKO CC Notes: 1. Caution: The Am28F010 must not be removed from (or inserted into) a socket when V the voltage difference between V PP time specification of 500 ns minimum tested with simulate open outputs. CC1 IH 3. Maximum active power usage is the sum ...

Page 24

... Read/Write PP V PPH Operations V Low V Lock-out Voltage LKO CC Notes: 1. Caution: The Am28F010 must not be removed from (or inserted into) a socket when V the voltage difference between V PP time specification of 500 ns minimum tested with simulate open outputs. CC1 IH 3. Maximum active power usage is the sum ...

Page 25

... Figure 5. Am28F010—Average I TEST CONDITIONS Device Under Test C L 6.2 k Note: Diodes are IN3064 or equivalent Figure 6. Test Setup Frequency in MHz Active vs. Frequency 5.5 V, Addressing Pattern = Minmax CC Data Pattern = Checkerboar 5.0 V Test Condition 2.7 k Output Load Output Load Capacitance, C (including jig capacitance) ...

Page 26

... V for a logic “0”. Input pulse rise and fall times are 10 ns. -70 Min 70 Max 70 Max 70 Max 35 Min 0 Max 20 Min 0 Max 20 Min 0 Min 6 Min 50 Am28F010 Test Points 1.5 V Input Output 11559H-15 Am28F010 Speed Options -90 -120 -150 -200 90 120 150 200 90 120 150 200 90 120 150 200 ...

Page 27

... Chip-Enable Controlled Writes: Write operations are driven by the valid combination of Chip-Enable and Write-Enable. In systems where Chip-Enable defines the Write Pulse Width (within a longer Write-Enable timing waveform) all set-up, hold and inactive Write-Enable times should be measured relative to the Chip-Enable waveform. 4. Not 100% tested. Am28F010 Speed Options -70 -90 Min ...

Page 28

... Changing from Changing from Does Not Apply Center Line is High Impedance State (High Z) Data Outputs Valid Enabled Addresses Stable AVAV GLQV ELQV CE t AXQX GLQX OLZ ELQX LZ Output Valid AVQV ACC Am28F010 OUTPUTS Changing, State Unknown Standby, Power-down t EHQZ ( GHQZ ( High Z 11559H-16 ...

Page 29

... PP V PPL Figure 8. AC Waveforms for Erase Operations Erase Erase-Verify Command Erasure Command AVWL WHEH CH t WHWH2 GHWL OES WHWL WPH WHDX DH DATA IN DATA IN = 20h = 20h Am28F010 Erase Standby, Verification Power-down AVAV WLAX EHQZ DF t WHGL GHQZ GLQV GLQX OLZ AXQX ...

Page 30

... Figure 9. AC Waveforms for Programming Operations 30 Program Command Latch Address Programming and Data Command WLAX WHEH CH t WHWH1 GHWL OES WHWL WPH WHDX DH DATA IN DATA IN = 40h Am28F010 Programming Standby, Verify Verification Power-down AVAV GHQZ DF t WHGL GHQZ GLQV GLQX AXQX OH VALID DATA IN = DATA ...

Page 31

... Excludes 00h programming prior to erasure 2 12.5 sec Excludes system-level overhead Cycles Parameter = 5.0 V, one pin at a time. CC Test Conditions OUT 25° 1.0 MHz. A Test Conditions 150 C 125 C Am28F010 Comments Min Max ) –1 –1 1 –100 mA +100 mA Typ Max Unit Min Unit ...

Page 32

... SEATING PLANE .015 .016 .060 .022 .009 .015 .125 .140 .080 .095 SEATING PLANE .013 .021 .050 REF. Am28F010 .600 .625 .009 .015 .630 .700 0 10 16-038-S_AG PD 032 EC75 5-28-97 lv .042 .056 .400 REF. .490 .530 16-038FPO-5 PL 032 ...

Page 33

... PHYSICAL DIMENSIONS TS032—32-Pin Standard Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 1 1.20 MAX 18.30 18.50 19.80 20. Am28F010 0.95 1.05 7.90 8.10 0.50 BSC 0.05 0.15 0.08 16-038-TSOP-2 0.20 TS 032 0.10 DA95 3-25-97 lv 0.21 0.50 0.70 33 ...

Page 34

... PHYSICAL DIMENSIONS TSR032—32-Pin Reversed Thin Small Outline Package (measured in millimeters) Pin 1 I.D. 1 1.20 MAX 34 18.30 18.50 19.80 20. 0.50 0.70 Am28F010 0.95 1.05 7.90 8.10 0.50 BSC 0.05 0.15 16-038-TSOP-2 0.08 TSR032 0.20 DA95 0.10 3-25-97 lv 0.21 ...

Page 35

... REVISION SUMMARY FOR AM28F010 Revision G+1 Distinctive Characteristics: High Performance: The fastest speed option available is now 70 ns. General Description: Paragraph 2: Changed fastest speed option to 70 ns. Product Selector Guide: Added -70, deleted -95 and -250 speed options. Ordering Information, Standard Products: The -70 speed option is now listed in the example. ...

Related keywords