LC72146 Sanyo Semiconductor Corporation, LC72146 Datasheet
LC72146
Available stocks
Related parts for LC72146
LC72146 Summary of contents
Page 1
... Ordering number : ENN4922D Overview The LC72146 is a PLL frequency synthesizer LSI circuit for electronic tuning in car stereo systems. The LC72146 supports the construction of high-performance, multi- functional electronic tuning systems for the VHF MW, and LW bands. Features • High-speed programmable dividers for — 160 MHz on FMIN using pulse swallower — ...
Page 2
... Package Dimensions unit: mm 3067A-DIP24S [LC72146] 21 0.9 (0.71) 1.78 0.48 0.95 unit: mm 3175B-SSOP24 [LC72146V] LC72146, 72146M, 72146V unit: mm 3112A-MFP24S 24 1 SANYO: DIP24S SANYO: SSOP24 [LC72146M 0.15 12.5 1.0 (0.75) 0.35 SANYO: MFP24S No. 4922-2/22 ...
Page 3
... V 3-3 IN Input amplitude 5-3 IN Data set up time t SU Data hold time t HD LC72146, 72146M, 72146V = Symbol Conditions V max max CE, CL max XIN, FMIN, AIN, AMIN, HCTR/I-6, LCTR/I-7, I/O-4, I/O max I/O-1 to I/O max max XOUT, I/O-4, I/O-5, O-6, PD0, PF1, AIN ...
Page 4
... Output high-level voltage Output low-level voltage Input high-level current Input low-level current LC72146, 72146M, 72146V Conditions * DO, CL; Depends on pull-up resistor = Conditions XIN FMIN AMIN HCTR/I-6 LCTR/I-7 AIN CE, CL, DI, LCTR/I 0 PD0, PD1, I/O-4, I/O-5, O AIN 0 PD0, PD1, I/O- I/O-5, O-6, O AIN 2 I/O-1 to I/O-3 ...
Page 5
... Xtal = 7.2 MHz 160 MHz mVrms MHz mVrms PLL inhibited, DD crystal oscillator running (Xtal = 7.2 MHz PLL inhibited, crystal oscillator stoped LC72146, 72146M, 72146V REFERENCE DIVIDER SWALLOW COUNTER 1/16, 1/17, 4bits 12bits PROGRAMMABLE DIVIDER DATA SHIFT REGISTER LATCH I/O-1 I/O-2 I/O-3 I/O-4 ...
Page 6
... Divisor value range 4095 • This pin must be set high to input serial data to the LC72146 DI pin or to output serial data from the DO pin. • Inputs the clock used for data synchronization when inputting serial data to the LC72146 DI pin or outputting Clock serial data from the DO pin ...
Page 7
... I/O-5 in the serial data sent from the controller. • The LC72146 latches the OUT6 bit in the serial data and outputs it from pin O-6. • The LC72146 latches the OUT7 bit in the serial data and outputs it from pin O-7. • Outputs a time base signal (8 Hz) when TBC is set to 1. ...
Page 8
... Continued from preceding page. Number Symbol General-purpose 13 LCTR/I-7 LC72146, 72146M, 72146V Type Function • LCTR is selected when CTS1 is set to 0. • If the CTS0 bit in the serial data is set to 1: • The circuit operates in frequency measurement mode. • nput frequency range 500 kHz • ...
Page 9
... Functional Description Serial Data Input The LC72146 operating parameters are initialized by two 40-bit data words on the serial data input, DI, as shown in Figure 1 and Figure 2 and Table 1. Address First Data In1 Address First Data In2 LC72146, 72146M, 72146V Figure 1 Input Data Word IN1 ...
Page 10
... When the PLL is disabled, the programmable divider is stopped, AMIN and FMIN are pulled to ground, and the charge-pump outputs become high impedance. LC72146, 72146M, 72146V Function SNS LSB SNS Input port Input frequency range (MHz) FMIN 1 AMIN 0 AMIN Charge pump state High impedance ...
Page 11
... When CTE is 0 the input is pulled down, and when CTP not. (Wait time ms.) CTP must be set least 4 ms before CTE is set to 1. CTP, CTC The input sensitivity can be reduced by setting CTC to 1. (Sensitivity rms) LC72146, 72146M, 72146V Function DT0 DO 0 Unlock flag ...
Page 12
... When TBC is 1 the OUT7 data will be invalid. TBC is set the power-on reset. Test data TEST0 to Bits TEST0 to TEST2 are used for in-factory device testing. Set them all to 0. They are set to zero after a (15) TEST2 power-on reset. LC72146, 72146M, 72146V Function UL0 Phase error 0 Stopped 1 ...
Page 13
... Bits C0 to C19 are the latched contents of the 20-bit binary counter. C19 is the MSB the LSB. Serial Data Input/Output Mode Selection The LC72146 use the CCB (computer control bus) serial data format. The first eight bits form the address, shown in Figure 6, used to select the mode of operation as shown in Table 13. ...
Page 14
... Programmable Divider The configuration of the programmable divider is shown in Figure 7. The input mode selection is shown in Table 14, and the input sensitivity, in Table 15. 4bits (A) FMIN Swallow (B) Counter AMIN Table 14 Programmable Divider Selection DVS SNS Note: = don’t care LC72146, 72146M, 72146V > ...
Page 15
... LCTR pin signal. The counter is started by setting the serial data CTE bit to 1. While serial data is latched in the LC72146 when CE falls from high to low, input to the HCTR or the LCTR pin must be provided within the waiting period that follows CE being set low ...
Page 16
... H To implement the integrating count operation leave CTE set to 1. When the serial data (IN1) is transmitted again, the general-purpose counter will start to measure the input again and the result will be added to the count. LC72146, 72146M, 72146V Input pin Measurement mode HCTR ...
Page 17
... When unlock is detected following a channel change, PDS (the sub-charge pump) operates. The value of R1 changes to R1M // R1S (R1S ≈ 100 Ω), as shown in Figure 10, decreasing the low-pass filter time-constant and accelerating PLL locking. PDO PDS R1S LC72146, 72146M, 72146V DLC (MAIN) (MAIN) DZ1 PDS ...
Page 18
... RF leakage from the mixer to the VCO to modulate the VCO in popularly-priced models when a strong RF input is applied. When the dead zone is small an output that compensates for this problem is generated, and this output may itself modulate the VCO and generate beating with the RF frequency. LC72146, 72146M, 72146V Charge pump Dead zone DZA ON/ON – ...
Page 19
... IF counting using HCTR or LCTR The LC72146 can perform IF count tuning when connected (station detector) signal from an IF IC. IF counting should start when the SD signal becomes active. Note on IF counting: The SD (station detect) signal must be used in conjunction with IF counting. ...
Page 20
... Since the grounding points for the clock time base output pin and the low-pass filter transistor are a common point within the IC, current fluctuations in the clock time base output pin must be kept to a minimum to limit influencing the low-pass filter. LC72146 LC72146, 72146M, 72146V FMV CC XOUT XIN ...
Page 21
... Serial Data Timing When CL is stopped at the low level Internal data latch When CL is stopped at the high level Internal data latch LC72146, 72146M, 72146V Old New Old New No. 4922-21/22 ...
Page 22
... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2001. Specifications and information herein are subject to change without notice. LC72146, 72146M, 72146V PS No. 4922-22/22 ...