M37281EKSP Renesas Electronics Corporation., M37281EKSP Datasheet
M37281EKSP
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M37281EKSP Summary of contents
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... They have a OSD function and a data slicer func- tion useful for a channel selection system for TV with a closed caption decoder. The feautures of the M37281EKSP is similar to those of the M37281MKH-XXXSP except that the chip has a built-in PROM which can be written electrically. The difference between M37281MAH– ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP TABLE OF CONTENTS 1. DESCRIPTION .......................................................................... 1 2. FEATURES ................................................................................ 1 3. APPLICATION ........................................................................... 1 4. PIN CONFIGURATION .............................................................. 3 5. FUNCTIONAL BLOCK DIAGRAM ............................................. 4 6. PERFORMANCE OVERVIEW .................................................. 5 7. PIN DESCRIPTION ................................................................... 7 8. FUNCTIONAL DESCRIPTION ................................................ 11 8.1 CENTRAL PROCESSING UNIT (CPU) ............................. 11 8.2 MEMORY .......................................................................... 12 8.3 INTERRUPTS .................................................................... 21 8.4 TIMERS ............................................................................. 26 8.5 SERIAL I/O ........................................................................ 30 8 ...
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... P0 /PWM3 /OUT2 0 P1 /SCL1 1 P1 /SCL2 2 P1 /SDA1 3 P1 /SDA2 /INT3/ /PWM7 3 P3 /AD7 0 P3 /AD8 1 RESET P6 /OSC2/X 4 COUT P6 /OSC1/X 3 CIN V CC MFH/MKH-XXXSP. This pin is AVcc pin of M37281EKSP. But NC pin of M37281MAH/MFH/MKH-XXXSP is not connect in the IC. You can apply to Vcc. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 5. FUNCTIONAL BLOCK DIAGRAM Fig. 5.1 Functional Block Diagram of M37281 Rev.1.01 2003.07.16 page 4 of 170 ...
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... Table 6.1 Performance Overview Parameter Number of basic instructions Instruction execution time Clock frequency M37281MAH-XXXSP Memory size ROM M37281MFH-XXXSP M37281MKH-XXXSP, M37281EKSP M37281MAH-XXXSP,M37281MFH-XXXSP RAM M37281MKH-XXXSP, M37281EKSP OSD ROM (character font) OSD ROM (color dot font) OSD RAM (SPRITE) OSD RAM (character) P0 – –P0 Input/Output 0 2 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Table 6.2 Performance Overview Parameter Number of display characters OSD function Dot structure Kinds of characters Kinds of character sizes Character font coloring Display position Power source voltage In high-speed OSD ON Power mode (Analog output) dissipation OSD ON (Digital output) OSD OFF ...
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... I/O synchronous clock input/output Rev.1.01 2003.07.16 page 7 of 170 Functions Apply voltage ± (typical ...M37281EKSP ( Connected enter the reset state, the reset input pin must be kept at a LOW for more (under normal V conditions more time is needed for the quartz-crystal oscillator to stabilize, this LOW condition should be maintained for the required time ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Table 7.2 Pin Description (continued) Input/ Pin Name Output P5 /R/R1, Output port P5 Output 2 P5 /G/G1, 3 OSD output Output P5 /B/B1 /OUT1 5 P6 /OSC1/ 3 Input port P6 Input X , CIN Clock input for OSD Input P6 /OSC2/ 4 Clock output for OSD ...
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... AD8 1 N-channel open-drain output Ports P0 – – Note1 : Each port is also used as follows : P0 –P0 : PWM4–PWM6 –P0 : PWM0–PWM3 M37281EKSP, does not have the diode side with N-channel open-drain output Port P1 - Note : Each port is also used as follows : P1 : SCL1 SCL2 SDA1 SDA2 4 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP OUT CLK Direction register Data bus SYNC SYNC Internal circuit Ports P4 – Data bus Ports P5 – Internal circuit Fig. 7.2 I/O Pin Block Diagram (2) Rev.1.01 2003.07.16 page 10 of 170 Port P5 5 Schmidt input SYNC SYNC Internal circuit ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8. FUNCTIONAL DESCRIPTION 8.1. CENTRAL PROCESSING UNIT (CPU) This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 <Software> User’s Manual for de- tails on the instruction set. ...
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... The M37281MAH-XXXSP has 40K-byte program area and M37281MFH-XXXSP has 60K-byte program area. The M37281MKH -XXXSP has 56K-byte program area and 24K-byte data-dedicated area. For the M37281EKSP, the two area (60K, 24K + 56K) can be swithed each other by setting the bank control register. 8.2.4 OSD RAM RAM for display is used for specifying the character codes and col- ors to display ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP AH 00BF 00FF M37281MAH-XXXSP, 0100 M37281MFH-XXXSP RAM (1088 bytes OSD RAM (Character) (1536 bytes) (Note 1000 M37281MFH-XXXSP ROM (60K bytes) 6000 M37281MAH-XXXSP ROM (40K bytes) FF00 FFFF Fig. 8.2.2 Memory Map (M37281MAH-XXXSP,M37281MFH-XXXSP) Rev.1.01 2003.07.16 page 13 of 170 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.2.10 Expansion ROM (only M37281MKH- XXXSP/M37281EKSP) The M37281MKH-XXXSP/M37281EKSP can use 5-bank (total 20K bytes) expansion ROM (4K bytes each bank) by setting the bank register. The expansion ROM is assigned to address 1B000 The contents of each bank in the expansion ROM are read by setting the bank register and accessing addresses 1000 expansion ROM is not programmable, use it as data-dedicated area ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Register Port P1 (P1 Port P1 direction register (D1 Port P4 direction register (D4 Port P6 (P6 Port P7 (P7 OSD control register 1 ( Block control register 2 ( Block control register 11 ( Block control register 14 ( Fig. 8.2.4 Memory Map of Special Function Register 1 (SFR1) (1) Rev.1.01 2003.07.16 page 15 of 170 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Caption data register 2 (CD2 Caption Position register (CPS Data slicer test register Data slicer test register Sync signal counter register (HC Clock run-in detect register (CRD address register (S0D status register (S1 clock control register (S2 register 2 (IREQ2) Interrupt request ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP I SFR2 area (addresses 200 Address Register 200 PWM0 register (PWM0) 16 201 PWM1 register (PWM1) 16 202 PWM2 register (PWM2) 16 203 PWM3 register (PWM3) 16 204 PWM4 register (PWM4) 16 205 PWM5 register (PWM5) 16 205 PWM6 register (PWM6) 16 207 PWM7 register (PWM7) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Vertical position register 1 221 Vertical position register Vertical position register 1 225 16 6 226 Vertical position register Vertical position register 1 229 16 10 22A 22C Vertical position register Vertical position register 22F Vertical position register Vertical position register 2 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP I SFR2 area (addresses 240 Register Address 240 16 241 16 Color pallet register 1 (CR1) 242 Color pallet register 2 (CR2) 16 243 16 Color pallet register 3 (CR3) 244 Color pallet register 4 (CR4) 16 245 16 Color pallet register 5 (CR5) 246 Color pallet register 6 (CR6) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Register Fig. 8.2.9 Internal State of Processor Status Register and Program Counter at Reset Rev.1.01 2003.07.16 page 20 of 170 < > “ 0 ” “ 1 ” “ 1 ” “ 0 ” ) Bit allocation < > : “ 0 ” “ 1 ” State immediately after reset ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.3 INTERRUPTS Interrupts can be caused by 19 different sources consisting of 3 ex- ternal, 14 internal, 1 software, and reset. Interrupts are vectored in- terrupts with priorities as shown in Table 8.3.1. Reset is also included in the table because its operation is similar to an interrupt. When an interrupt is accepted, x The contents of the program counter and processor status register are automatically stored into the stack ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP (4) Serial I/O Interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(X )/4096 • SPRITE OSD Interrupt IN The f (X )/4096 interrupt occurs regularly with a f(X IN riod. Set bit 0 of the PWM mode register 1 to “0.” ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Interrupt Request Register Interrupt request register 1 (IREQ1) [Address 00FC “0” can be set by software, but “1” cannot be set. Fig. 8.3.2 Interrupt Request Register 1 Interrupt Request Register Interrupt request register 2 (IREQ2) [Address 00FD Timer 5 • 6 interrupt 7 8: “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Interrupt Control Register Fig. 8.3.4 Interrupt Control Register Interrupt Control Register Fig. 8.3.5 Interrupt Control Register 2 Rev.1.01 2003.07.16 page 24 of 170 Interrupt control register 1 (ICON1) [Address 00FE Name Functions 0 : Interrupt disabled Timer 1 interrupt enable bit (TM1E) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Fig. 8.3.6 Interrupt Input Polarity Register Rev.1.01 2003.07.16 page 25 of 170 Name Functions “ ” “ ” A-D conversion • INT3 interrupt source selection bit (AD/INT3SEL — — ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.4 TIMERS This microcomputer has 6 timers: timer 1, timer 2, timer 3, timer 4, timer 5, and timer 6. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Timer mode register 1 (TM1) [Address 00F4 Timer 2 count stop bit (TM13 Timer 1 count source selection bit 2 (TM15 Fig. 8.4.1 Timer Mode Register 1 Rev.1.01 2003.07.16 page 27 of 170 ] Functions 0: f(X )/16 or f(X )/16 (See note) IN CIN 1: Count source selected by bit 5 of TM1 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Timer Mode Register Timer mode register 2 (TM2) [Address 00F5 B 0 Timer 3 count source selection bit (TM20 Timer 4 count source selection bits (TM21, TM24) Timer 3 count stop bit 2 (TM22) Timer 4 count stop bit 3 (TM23) 5 Timer 5 count stop bit ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP CM7 Fig. 8.4.3 Timer Block Diagram Rev.1.01 2003.07.16 page 29 of 170 TM10 Timer 2 latch ( Timer 2 ( TM13 x x T3CS Timer 3 ( Timer 4 (8) TM21 TM23 TM16 TM25 ) Timer 6 latch ( TM26 Reset STP instruction ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.5 SERIAL I/O This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchro- nous clock I/O pin (S ), and data output pin (S ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Internal clock : The serial I/O counter is set to “7” during the write cycle into the serial I/O register (address 0214 clock goes “H” forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the S rection can be selected by bit 5 of the serial I/O mode register ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Serial I/O mode register (SM) [Address 0213 Internal synchronous clock selection bits (SM0, SM1) Synchronous clock 2 selection bit (SM2) 3 Port function selection bit (SM3) 4 Port function selection bit (SM4) Transfer direction 5 selection bit (SM5 (SM6 “ ” ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 2 8.6 MULTI-MASTER I C-BUS INTERFACE 2 The multi-master I C-BUS interface is a serial communications cir- 2 cuit, conforming to the Philips I C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 2 8.6 Data Shift Register 2 The I C data shift register (S0 : address 00F6 register to store receive data and write transmit data. When transmit data is written into this register transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 2 8.6 Address Register 2 The I C address register (address 00F7 ) consists of a 7-bit slave 16 address and a read/write bit. In the addressing mode, the slave ad- dress written in this register is compared with the address data to be received immediately after the START condition are detected. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 2 8.6 Clock Control Register 2 The I C clock control register (address 00FA control, SCL mode and SCL frequency. (1) Bits SCL Frequency Control Bits (CCR0–CCR4) These bits control the SCL frequency. (2) Bit 5: SCL Mode Specification Bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 2 8.6 Control Register 2 The I C control register (address 00F9 ) controls the data commu- 16 nication format. (1) Bits Bit Counter (BC0–BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Control Register control register (S1D) [Address 00F9 Connection control bits 2 Fig. 8.6 Control Register Rev.1.01 2003.07.16 page 38 of 170 ] 16 Name Functions Bit counter (Number of transmit/recieve bits (BC0 to BC2 C-BUS interface use 0: Disabled enable bit (ESO) 1: Enabled ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 2 8.6 Status Register 2 The I C status register (address 00F8 ) controls the I 16 face status. The low-order 4 bits are read-only bits and the high- order 4 bits can be read out and written to. (1) Bit 0: Last Receive Bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP (8) Bit 7: Communication Mode Specification Bit (master/slave specification bit: MST) This bit is used for master/slave specification for data communica- tion. When this bit is “0,” the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.6.6 START Condition Generation Method 2 When the ESO bit of the I C control register (address 00F9 2 execute a write instruction to the I C status register (address 00F8 to set the MST, TRX and BB bits to “1.” A START condition will then be generated. After that, the bit counter becomes “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.6.8 START/STOP Condition Detect Conditions The START/STOP condition detect conditions are shown in Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table 8.6.3 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.6.10 Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz and in the ACK return mode is shown below. Œ Set a slave address in the high-order 7 bits of the I register (address 00F7 ) and “0” in the RBW bit. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP S Slave address R/W 7 bits “0” (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W 7 bits “1” (2) A master-receiver receives data from a slave-transmitter Slave address S R/W 1st 7 bits 7 bits “0” (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP (3) RESTART condition generating procedure ŒProcedure example (The necessary conditions of the generating procedure are described as the following to ‘.) Execute the following procedure when the PIN bit is “0.” • • LDM #$00, S1 (Select slave receive mode) LDA — ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.7 PWM OUTPUT CIRCUIT This microcomputer is equipped with eight 8-bit PWMs (PWM0– PWM7). PWM0–PWM7 have the same circuit structure and an 8-bit resolution with minimum resolution bit width and repeat pe- riod of 1024 s (for f MHz Figure 8.7.1 shows the PWM block diagram. The PWM timing gen- erating circuit applies individual control signals to PWM0– ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Data bus X IN PWM0 register (Address 0200 b7 PWM1 register (Address 0201 PWM2 register (Address 0202 PWM3 register (Address 0203 PWM4 register (Address 0204 PWM5 register (Address 0205 PWM6 register (Address 0206 PWM7 register (Address 0207 Selection gate: ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Fig. 8.7.2 PWM Timing Rev.1.01 2003.07.16 page 48 of 170 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP PWM Mode Register PWM mode register 1 (PN) [Address 020A Nothing is assigned. These bits are write disable bits. Fig. 8.7.3 PWM Mode Register PWM Mode Register Fig. 8.7.4 PWM Mode Register 2 Rev.1.01 2003.07.16 page 49 of 170 ] 16 Name ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.8 A-D CONVERTER 8.8.1 A-D Conversion Register (AD) A-D conversion reigister is a read-only register that stores the result of an A-D conversion. This register should not be read during A-D conversion. 8.8.2 A-D Control Register (ADCON) The A-D control register controls A-D conversion. Bits this register select analog input pins ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP A-D Control Register Fig. 8.8.2 A-D Control Register Rev.1.01 2003.07.16 page 51 of 170 A-D control register (ADCON) [Address 00EF B Name Functions 0 Analog input pin selection bits AD1 2 (ADIN0 to ADIN2 AD2 AD3 AD4 AD5 AD6 AD7 AD8 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.8.6 Conversion Method Œ Set bit 7 of the interrupt input polarity register (address 0212 “1” to generate an interrupt request at completion of A-D conver- sion. Set the A-D conversion · INT3 interrupt request bit to “0” (even when A-D conversion is started, the A-D conversion · ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.8.8 Definition of A-D Conversion Accuracy The definition of A-D conversion accuracy is described below (refer to Figure 8.8.4). Accuracy is shown the difference between measurement result out- put code and output code which is expected for A-D conversion whose specification is ideal by using LSB. ...
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... Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program not set the same ROM correction address to vectors 1 and 2. 4: For the M37281MKH-XXXSP and M37281EKSP, when using the ex- pansion ROM (BK7 = “1”), the ROM correction function do not oper- ate used for addresses 1000 to1FFF ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.10 DATA SLICER This microcomputer includes the data slicer function for the closed caption decoder (referred to as the CCD). This function takes out the caption data superimposed in the vertical blanking interval of a com- posite video signal. A composite video signal which makes the sync chip’ ...
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... HOLD Pull- kΩ or more. (8) Only M37281EKSP have AVCC pin. This pin is non-connection pin in M37281MAH-XXXSP, M37281MFH-XXXSP, M37281MKH-XXXSP. But NC pin of M37281MAH-XXXSP, M37281MFH-XXXSP, M37281MKH-XXXSP is not connect in the IC. You can apply to Vcc. Fig. 8.10.3 Termination of Data Slicer Input/Output Pins when Timing Signal Generating Circuit State Rev ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Figures 8.10.4 and 8.10.5 the data slicer control registers. Data Slicer Control Register Fig. 8.10.4 Data Slicer Control Register 1 Data Slicer Control Register Fig. 8.10.5 Data Slicer Control Register 2 Rev.1.01 2003.07.16 page 57 of 170 Data slicer control register 1(DSC1) [Address 00E0 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.10.2 Clamping Circuit and Low-pass Filter The clamp circuit clamps the sync chip part of the composite video signal input from the CV pin. The low-pass filter attenuates the noise IN of clamped composite video signal. The CV IN video signal is input requires a capacitor (0.1 µF) coupling outside. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.10.5 Timing Signal Generating Circuit This circuit generates a reference clock which is 832 times as large as the horizontal synchronous signal frequency. It also generates various timing signals on the basis of the reference clock, horizontal synchronous signal and vertical synchronizing signal. The circuit ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.10.6 Data Slice Line Specification Circuit (1) Specification of Data Slice Line This circuit decides a line on which caption data is superimposed. The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2 line for a period of 1 field), and both fields (F1 and F2) are sliced their data ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Caption Position Register Fig. 8.10.9 Caption Position Register Table 8.10.1 Specification of Data Slice Line CPS Field and Line to Be Sliced Data b7 b6 • Both fields of F1 and • Line 21 and a line specified by bits CPS (total 2 lines) (See note 2) • ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.10.7 Reference Voltage Generating Circuit and Comparator The composite video signal clamped by the clamping circuit is input to the reference voltage generating circuit and the comparator. (1) Reference Voltage Generating Circuit This circuit generates a reference voltage (slice voltage) by us- ing the amplitude of the clock run-in pulse in line specified by the data slice line specification circuit ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.10.10 Data Clock Generating Circuit This circuit generates a data clock synchronized with the start bit detected in the start bit detecting circuit. The data clock stores cap- tion data to the 16-bit shift register. When the 16-bit data has been stored and the clock run-in determination circuit determines clock run-in, the caption data latch completion flag is set ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.10.11 16-bit Shift Register The caption data converted into a digital value by the comparator is stored into the 16-bit shift register in synchronization with the data clock. The contents of the high-order 8 bits of the stored caption data can be obtained by reading out data register 2 (address 00E3 and data register 4 (address 00E5 ) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.10.13 Synchronous Signal Counter The synchronous signal counter counts the composite sync signal taken out from a video signal in the data slicer circuit or the vertical synchronous signal count source. sep The count value in a certain time (T time) generated by f(X ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11 OSD FUNCTIONS Table 8.11.1 outlines the OSD functions. This OSD function can display the following: the block display (32 characters 16 lines), the SPRITE display. And besides, the func- tion can display the both display at the same time. There are 3 dis- play modes and they are selected by a block unit ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP The OSD circuit has an extended display mode. This mode allows multiple lines (16 lines or more displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display is terminated by software Fig. 8.11.1 Configuration of OSD Character Display Area Rev ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Fig. 8.11.2 Block Diagram of OSD Circuit Rev.1.01 2003.07.16 page 68 of 170 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP OSD Control Register OSD control register 1 (OC1) [Address 00CE B 0 OSD control bit 1 Scan mode selection 2 3 Flash mode selection 4 Automatic solid space 5 Vertical window/blank control bit (OC15 Notes 1 : Even this bit is switched during display, the display screen Fig ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Display mode selection bits (BCi0, BCi1 Pre-divide ratio selection bit (BCi5, BCi6) 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. Notes OSD clock cycle divided in pre-divide circuit This character size is available only in Layer 2. At this time, set layer 1’s pre-divide ratio = 2, layer 1’ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.1 Triple Layer OSD Three built-in layers of display screens accommodate triple display of channels, volume, etc., closed caption, and SPRITE displays within layers The layer to be displayed in each block is selected by bit the OSD control register 2 for each display mode (refer to Figure 8.11.7). ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Block Fig. 8.11.5 Triple Layer OSD “ ” “ ” ’ ’ “ ” “ 0 ” Fig. 8.11.6 Display Example of Triple Layer OSD Rev.1.01 2003.07.16 page 72 of 170 Layer layer ’ ’ “ ” “ 1 ” ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP OSD Control Register Fig. 8.11.7 OSD Control Register 2 Rev.1.01 2003.07.16 page 73 of 170 OSD control register 2 (OC2) [Address 0215 ] 16 B Name Functions 0, 1 Display layer b1 b0 Layer 1 selection bits 0 0 CC, OSD, CDOSD 0 1 CC, OSD (OC20, OC21) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.2 Display Position The display start positions of characters are specified by a block. There are 16 blocks, blocks characters can be displayed in each block (refer to “8.11.6 Memory for OSD”). The display position of each block can be set in both horizontal and vertical directions by software ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP The display start position in the vertical direction is determined by counting the horizontal sync signal ( this time, when V SYNC and H are positive polarity (negative polarity), it starts to count SYNC the rising edge (falling edge signal from after fixed cycle of ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP The vertical start position for each block can be set in 1024 steps (where each step cycle)) as values “ SYNC in vertical position register 16) (addresses 0220 and values “00 ” to “03 ” in vertical position register 16 (addresses 0230 to 023F ). The vertical position registers are ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP The horizontal display position is common to all blocks, and can be set in 256 steps (where 1 step OSC OSC cycle for display) as values “00 ” to “FF ” in bits the hori zontal position register (address 00CF ). The horizontal position reg- 16 ister is shown in Figure 8 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.3 Dot Size The dot size can be selected by a block unit. The dot size in vertical direction is determined by dividing H in the vertical dot size con- SYNC trol circuit. The dot size in horizontal is determined by dividing the following clock in the horizontal dot size control circuit : the clock gained by dividing the OSD clock source (data slicer clock, OSC1, main clock) in the pre-divide circuit ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.4 Clock for OSD As a clock for display to be used for OSD possible to select one of the following 3 types. • Data slicer clock output from the data slicer (approximately 26 MHz) • Clock from the LC oscillator supplied from the pins OSC1 and OSC2 • ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Data slicer circuit “00” 32kHz “10” LC CS2 Ceramic • quartz-crystal “11” Oscillating mode for OSD Note : To use data slicer clock, set bit 0 of data slicer control register 1 to “1.” Fig. 8.11.17 Block Diagram of OSD Selection Circuit Rev ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.5 Field Determination Display To display the block with vertical dot size of 1/2H, whether an even field or an odd field is determined through differences in a synchro- nizing signal waveform of interlacing system. The dot line (re- fer to Figure 8.11.19) corresponding to the field is displayed alter- nately ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Both H signal and V signal are negative-polarity input SYNC SYNC H SYNC V and SYNC (n–1) field V SYNC (Odd-numbered) control signal in microcom- puter (n) field Upper : (Even-numbered) V signal SYNC Lower : V control SYNC signal in (n+1) field micro- (Odd-numbered) computer When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 020A ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.6 Memory for OSD There are 2 types of memory for OSD : OSD ROM (addresses 10800 to 157FF and 18000 to 1ACFF acter dot data and OSD RAM (addresses 0700 0800 to 0FDF ) used to specify the kinds of display characters display colors, and SPRITE display. The following describes each type of memory ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Line number = “ ” “ ” code = “ ” “ ” ( “ ” “ Area bit = Area 0 Area Fig. 8.11.21 Color Dot Font Data Storing Address Rev.1.01 2003.07.16 page 84 of 170 ” “ ” Line b 0 number ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP (2) OSD RAM (addresses 0700 to 07A7 16 16 The OSD RAM for SPRITE consisting of 3 planes, is assigned to addresses 0700 to 07A7 . Each plane corresponds to each color 16 16 pallet selection bit and the color pallet of each dot is determined from among 8 kinds. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Table 8.11.4 Contents of OSD RAM (SPRITE) Line (from top) Dot (from left) Line 1 Dots Dots Line 2 Dots Dots Line 19 Dots Dots Dots Line 20 Dots Plain 780 781 Line 1 782 783 Line 2 7A4 7A5 Line 19 7A6 7A7 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Table 8.11.5 Contents of OSD RAM (Character) Block Display Position (from left) 1st character 2nd character Block 1 : 31st character 32nd character 1st character 2nd character Block 2 : 31st character 32nd character 1st character 2nd character Block 3 : 31st character ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Table 8.11.6 Contents of OSD RAM (continued) Block Display Position (from left) 1st character 2nd character Block 11 : 31st character 32nd character 1st character 2nd character Block 12 : 31st character 32nd character 1st character 2nd character Block 13 : 31st character ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Note: Do not read from/write to the addresses in Table 8.11.7. Table 8.11.7 List of Access Disable Addresses 0860 to 087F 0C60 16 16 08E0 to 08FF 0CE0 10 16 0960 to 097F 0D60 16 16 09E0 to 09FF 0DE0 16 16 0A60 to 0A7F 0E60 16 16 0AE0 to 0AFF ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Blocks RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 RC17 RC16 RC15 RC14 RC13 RC12 RC11 RC10 Character code CC mode Bit Bit name Function RF0 Character code Specify (Low-order 8 bits) character code RF1 in OSD ROM RF2 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.7 Character Color As shown in Figure 2.11.24, there are 16 built-in color pallets. Color pallet 0 is fixed at transparent, and color pallet 8 is fixed at black. The remaining 14 colors can be set to any of the 64 colors available. The setting procedure for character colors is as follows: • ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Fig. 8.11.24 Color Code Selection Rev.1.01 2003.07.16 page 92 of 170 ( ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Dot area specified to color pallet 1 Dot area specified to color pallet 0 Fig. 8.11.25 Set of Color Pallet CDROM Mode Color pallet 1 (Transparent) Layer 1 (CC mode) Color pallet 2 (Blue Layer (OSD mode Fig. 8.11.26 Difference Between Color Code 0 (Transparent) and Transparent Setting of Other Color Codes Rev ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP OSD Control Register Fig. 8.11.27 OSD Control Register 3 Color Pallet Register Fig. 8.11.28 Color Pallet Register 15) Rev.1.01 2003.07.16 page 94 of 170 OSD control register 3 (OC3) [Address 0219 ] 16 B Name Functions 0 CC mode character color 0: Color code ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.9 OUT1, OUT2 Signals The OUT1, OUT2 signals are used to control the luminance of the video signal. The output waveform of the OUT1, OUT2 signals is controlled by bit 6 of the color code register i (refer to Figure 8.11.28 control bit (See ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.10 Attribute The attributes (flash, underline, italic) are controlled to the character font. The attributes to be controlled are different depending on each mode. CC mode .................... Flash, underline, italic for each character OSD mode ................. Border (all bordered, shadow bordered can ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP (a) Ordinary ( flash (e) Under line and Italic and flash Fig. 8.11.30 Example of Attribute Display (in CC Mode) Rev.1.01 2003.07.16 page 97 of 170 Bit (RC16 Color code 1 Bit 6 Bit 4 (RC16) (RC14 (d) Under line and Italic (pre-divide ratio = flash Bit 6 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP (Refer to “8.11.10 Notes 5, 6” “ ” Fig. 8.11.31 Example of Italic Display Rev.1.01 2003.07.16 page 98 of 170 (Refer to “8.11.10 Notes 6, 7” 32nd character (See note ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP (4) Border The border is output only in the OSD mode. The all bordered (bordering around of character font) and the shadow bordered (bordering right and bottom sides of character font) are selected (refer to Figure 8.11.32) by bit 2 of the OSD control register 1 (refer to Figure 8 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Character font area 1 dot width of border Fig. 8.11.34 Border Area Character boundary Fig. 8.11.35 Border Priority Rev.1.01 2003.07.16 page 100 of 170 OSD mode 16 dots 1 dot width of border Character boundary Character boundary ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.11 Automatic Solid Space Function This function generates automatically the solid space (OUT1 or OUT2 blank output) of the character area in the CC mode. The solid space is output in the following area : • Any character area except character code “009 • ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.12 Multiline Display This microcomputer can ordinarily display 16 lines on the CRT screen by displaying 16 blocks at different vertical positions. In addition, it can display lines by using OSD interrupts. An OSD interrupt request occurs at the point at which display of each block has been completed. In other words, when a scanning line ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.13 SPRITE OSD Function This is especially suitable for cursor and other displays as its func- tion allows for display in any position, regardless of the validity of other OSDs or display positions. The SPRITE font is a RAM font consisting of 16 horizontal dots 20 vertical dots, three planes, and three bits of data per dot ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP SPRITE OSD Control Register Dot size selection Notes Pre-devided clock period for OSD Fig. 8.11.39 SPRITE OSD Control Register Rev.1.01 2003.07.16 page 104 of 170 SPRITE OSD control register (SC) [Address 0258 B Name Functions 0 SPRITE OSD 0: Stopped control bit ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP SPRITE Horizontal Position Register SPRITE horizontal position register 1 (HS1) [Address 0256 B 0 Horizontal display to start position 7 control bits of SPRITE OSD (HS10 toHS17) Notes 1: Do not set HS1 < “30 Fig. 8.11.40 SPRITE Horizontal Position Register 1 SPRITE Horizontal Position Register 2 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP SPRITE Vertical Position Register Fig. 8.11.42 SPRITE Vertical Position Register 1 SPRITE Vertical Position Register Fig. 8.11.43 SPRITE Vertical Position Register 2 Rev.1.01 2003.07.16 page 106 of 170 SPRITE vertical position register 1 (VS1) [Address 0254 B Name Functions Vertical display start position (low-order 8 bits) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.14 Window Function The window function can be set windows on-screen, and output OSD within only the area where the window is set. The ON/OFF for vertical window function is performed by bit 5 of OSD control register 1 and is used to select vertical window function or vertical blank function by bit 6 of OSD control register 2 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.15 Blank Function The blank function can output blank (OUT1) area on all sides (verti- cal and horizontal) of the screen. The ON/OFF for vertical blank function is performed by bit 5 of the OSD control register 1 and is used to select vertical window function or vertical blank function by bit 6 of the OSD control register 2 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Top Border Control Register Top border control register 1 (TB1) [Address 021C Notes 1: Do not set “00 Fig. 8.11.46 Top Border Control Register 1 Top Border Control Register Top border control register 2 (TB2) [Address 021E B 0, Control bits of ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Bottom Border Control Register Bottom border control register 1 (BB1) [Address 021D Notes 1: Set values fit for the following condition: Fig. 8.11.48 Bottom Border Control Register 1 Bottom Border Control Register Bottom border control register 2 (BB2) [Address 021F ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Left Border Control Register Fig. 8.11.50 Left BorderControl Register 1 Left Border Control Register Fig. 8.11.51 Left BorderControl Register 2 Rev.1.01 2003.07.16 page 111 of 170 Left border control register 1 (LB1) [Address 0250 B Name Functions 0 Left border position (low-order 8 bits) ...
Page 112
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Right Border Control Register Fig. 8.11.52 Right Border Control Register 1 Right Border Control Register Fig. 8.11.53 Right Border Control Register 2 Rev.1.01 2003.07.16 page 112 of 170 Right border control register 1 (RB1) [Address 0252 B Name Functions Control bits of ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.16 Raster Coloring Function An entire screen (raster) can be colored by setting the bits the raster color register. Since each of the OUT1, and OUT2 pins can be switched to raster coloring output, 64 raster colors can be obtained. When the character color/the character background color overlaps ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP < > Fig. 8.11.55 Example of Raster Coloring Rev.1.01 2003.07.16 page 114 of 170 “ ” “ ” “ ” “ ” Signals across A- Character color “RED” OUT1) : Border color “BLACK” (OUT1) : Background color “MAGENTA” OUT1 Raster color “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.17 Scan Mode This microcomputer has the bi-scan mode for corresponding double speed frequency. In the bi-scan mode, the vertical start display position and the vertical size is two times as compared with the normal scan mode. The scan mode is selected by bit 1 of the OSD control register 1 (refer to Figure 8 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.11.18 OSD Output Pin Control The OSD output pins R(R1), G(G1), B(B1) and OUT1 can also func- tion as ports Set the corresponding bit of the OSD port 2 5 control register (address 00CB ) to “0” to specify these pins as OSD 16 output pins, or set it to “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.12. SOFTWARE RUNAWAY DETECT FUNC- TION This microcomputer has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation, the following processing is done. Œ The CPU generates an undefined instruction decoding signal. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.13. RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic reso- nator is stable and the power source voltage ± hold the RESET pin at LOW for 2 µs or more, then return is to HIGH. Then, as shown in Figure 8.13.2, reset is released and the program starts form ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.14 CLOCK GENERATING CIRCUIT This microcomputer has 2 built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between and X ). Use the circuit constants in accordance with OUT CIN COUT the resonator manufacturer’s recommended values. No external re- sistor is needed between X ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP X X CIN COUT OSC1 oscillating mode selection bits (See notes OUT Internal system clock selection bit (See notes 1, 3) Main clock (X IN Internal system clock selection bit (Notes STP instruction Notes 1 : The value at reset is “0.” ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP WIT instruction 8 MHz oscillating 32 kHz oscillating φ is stopped (HIGH) Timer operating External INT, timer interrupt, or SI/O interrupt WIT instruction 8 MHz oscillating 32 kHz oscillating φ is stopped (HIGH) Timer operating (Note 3) WIT instruction 8 MHz stopped 32 kHz oscillating φ is stopped (HIGH) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 8.15. DISPLAY OSCILLATION CIRCUIT The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, a ceramic resonator quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 10. ABSOLUTE MAXIMUM RATINGS Parametear Symbol Power source voltage V , (See note ( Input voltage CNV Input voltage P0 – –P7 0 ______ RESET Output voltage P0 – OSC2 OUT Circuit current P5 – – Circuit current P5 –P5 OL1 2 P2 – Circuit current P1 – ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 12. ELECTRIC CHARACTERISTICS Symbol Parameter I Power source current CC V HIGH output voltage P5 – – LOW output voltage OUT CLK P1 – – LOW output voltage LOW output voltage P1 – Hysteresis (See note 6) RESET – V SYNC T+ T– INT3, TIM2, TIM3, S ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 1 Power source voltage A Vcc X IN 8.00 MHz OSC1 X OUT X CIN OSC2 32 kHz X COUT Vss Pin V is confirmed the operation and tested CC the current with a ceramic resonator. 3 5.0V Vcc Each output pin Vss Fig.12.1 Test circuit Rev.1.01 2003 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 13. ANALOG OUTPUT CHARACTERISTICS ( ± f MHz Symbol Parameter R Output resistance O V Output deviation OE T Settling time Fig.13.1 Analog Output Characteristics 14. A-D CONVERTER CHARACTERISTICS ( ± f MHz Symbol Parameter — Resolution — Absolute accuracy (excludig guantization error) T Conversion time ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 2 15. MULTI-MASTER I C-BUS BUS LINE CHARACTERISTICS Symbol t Bus free time BUF t Hold time for START condition HD; STA t LOW period of SCL clock LOW t Rising time of both SCL and SDA signals R t Data hold time HD; DAT t HIGH period of SCL clock ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 16. PROM PROGRAMMING METHOD The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a general- purpose PROM programmer using a special programming adapter. Product Name of Programming Adapter M37281EKSP PCA7400 The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 17. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: • Mask ROM Order Confirmation Form • Mark Specification Form • Data to be written to ROM, in EPROM form (52-pin DIP Type 27C101, three identical copies) or FDK Rev ...
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... P0 /PWM3 /OUT2 0 P1 /SCL1 1 P1 /SCL2 2 P1 /SDA1 3 P1 /SDA2 /INT3/ /PWM7 3 P3 /AD7 0 P3 /AD8 1 RESET P6 /OSC2/X 4 COUT P6 /OSC1/X 3 CIN V CC MFH/MKH-XXXSP. This pin is AVcc pin of M37281EKSP. But NC pin of M37281MAH/MFH/MKH-XXXSP is not connect in the IC. You can apply to Vcc. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Memory Map Rev.1.01 2003.07.16 page 131 of 170 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP AH M37281MFH-XXXSP 00BF 00FF 16 M37281MAH-XXXSP, 0100 16 M37281MFH-XXXSP RAM (1088 bytes OSD RAM (Character) (1536 bytes) (Note 1000 16 M37281MFH-XXXSP ROM (60K bytes) 6000 16 M37281MAH-XXXSP ROM (40K bytes) FF00 Interrupt vector area FFFF 16 Rev.1.01 2003.07.16 page 132 of 170 ROM correction function ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Memory Map of Special Function Register (SFR Register Port P1 (P1 Port P1 direction register (D1 Port P4 direction register (D4 Port P6 (P6 Port P7 (P7 OSD control register 1 ( Block control register 2 ( Block control register 14 ( Rev.1.01 2003.07.16 page 133 of 170 < > function bit : “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Caption data register 2 (CD2 Caption Position register (CPS Data slicer test register Data slicer test register Sync signal counter register (HC Clock run-in detect register (CRD address register (S0D status register (S1 clock control register (S2 register 2 (IREQ2) Interrupt request ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP I SFR2 area (addresses 200 Address Register 200 PWM0 register (PWM0) 16 201 PWM1 register (PWM1) 16 202 PWM2 register (PWM2) 16 203 16 PWM3 register (PWM3) 204 16 PWM4 register (PWM4) 205 16 PWM5 register (PWM5) 205 16 PWM6 register (PWM6) 207 PWM7 register (PWM7) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 221 Vertical position register Vertical position register 225 Vertical position register 226 Vertical position register Vertical position register 1 229 16 10 22A Vertical position register Vertical position register 22C Vertical position register Vertical position register Vertical position register 1 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP I SFR2 area (addresses 240 Register Address 240 16 241 16 Color pallet register 1 (CR1) 242 Color pallet register 2 (CR2) 16 243 16 Color pallet register 3 (CR3) 244 Color pallet register 4 (CR4) 16 245 16 Color pallet register 5 (CR5) 246 16 Color pallet register 6 (CR6) ...
Page 138
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Internal State of Processor Status Register and Program Counter at Reset Register Rev.1.01 2003.07.16 page 138 of 170 < < > “ 0 ” “ 1 ” “ 1 ” “ 0 ” ) Bit allocation > : “ 0 ” “ 1 ” State immediately after reset ...
Page 139
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows < > CPU mode register (CPUM) (CM) [Address 00FB B Processor mode bits (CM0, CM1) Stack page selection 2 bit (See note) (CM2 “ ” ...
Page 140
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Port Pi Direction Register Port P3 Direction Register Rev.1.01 2003.07.16 page 140 of 170 Addresses 00C1 Port Pi direction register (Di) (i=0,1,2) [Addresses 00C1 B Name Functions Port Pi input mode Port Pi direction register Port Pi output mode Port Pi input mode Port Pi output mode ...
Page 141
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Port P4 Direction Register OSD Port Control Register Rev.1.01 2003.07.16 page 141 of 170 0 Port P3 direction register (D4) [Address 00C9 B Name Functions 0 Fix this bit to “0” Nothing is assigned. These bits are write disable bits When these bits are read out, the values are “0.” ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP OSD Control Register Notes 1 : Even this bit is switched during display, the display screen Horizontal Position Register Notes 1. The setting value synchronizes with the V Rev.1.01 2003.07.16 page 142 of 170 OSD control register 1 (OC1) [Address 00CE Functions B Name ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Block control register i (BCi) (i=1 to 16) [Addresses 00D0 Display mode selection bits (BCi0, BCi1 Pre-divide ratio selection bit (BCi5, BCi6) 7 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is indeterminate. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Data Slicer Control Register Data Slicer Control Register Rev.1.01 2003.07.16 page 144 of 170 Data slicer control register 1(DSC1) [Address 00E0 B Name Functions Data slicer and timing signal 0 0: Stopped generating circuit control bit (DSC10) 1: Operating Selection bit of data slice reference ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Caption Position Register Sync Pulse Counter Register Rev.1.01 2003.07.16 page 145 of 170 Caption Position Register (CPS) [Address 00E6 16 B Name Functions 0 Caption position to bits(CPS0 to CPS4 Data is not latched yet and a Caption data latch completion flag 2 clock-run-in is not determined. ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Data Clock Position Register Rev.1.01 2003.07.16 page 146 of 170 0 1 Data clock position register (DPS) [Address 00EB B Name 0 Fix these bits to “1.“ 1,2 Fix this bit to “0.“ 3 Data clock position set bits (DPS3 to DPS7) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP A-D Control Register Rev.1.01 2003.07.16 page 147 of 170 A-D control register (ADCON) [Address 00EF B Name Functions 0 Analog input pin selection bits AD1 2 (ADIN0 to ADIN2 AD2 AD3 AD4 AD5 AD6 AD7 AD8 A-D conversion completion 0: Conversion in progress ...
Page 148
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Timer mode register 1 (TM1) [Address 00F4 Timer 2 count stop bit (TM13 Timer 1 count source selection bit 2 (TM15 Rev.1.01 2003.07.16 page 148 of 170 ] Functions 0: f(X )/16 or f(X )/16 (See note) IN CIN 1: Count source selected by bit 5 of TM1 0: Count source selected by bit 4 of TM1 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Timer Mode Register Timer mode register 2 (TM2) [Address 00F5 B 0 Timer 3 count source selection bit (TM20 Timer 4 count source selection bits (TM21, TM24) Timer 3 count stop bit 2 (TM22) Timer 4 count stop bit 3 (TM23) 5 Timer 5 count stop bit ...
Page 150
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Data Shift Register Rev.1.01 2003.07.16 page 150 of 170 data shift register (S0) [Address 00F6 ] 16 B Name Functions This is an 8-bit shift register to store to receive data and write transmit data. 7 Note: To write data into the data shift register after setting the MST bit to “ ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Control Register Connection control bits Rev.1.01 2003.07.16 page 151 of 170 status register (S1) [Address 00F8 16 Name Functions Last bit = “0” Last bit = “1” general call detected ( General call detected Address mismatch Address match Not detected ...
Page 152
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Clock Control Register Rev.1.01 2003.07.16 page 152 of 170 clock control register (S2) [Address 00FA ] 16 Functions B Name 0 SCL frequency control bits Register Standard to (CCR0 to CCR4) value clock mode Setup disabled Setup disabled 03 Setup disabled 04 Setup disabled 05 100 06 83.3 ...
Page 153
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Interrupt Request Register Interrupt request register 1 (IREQ1) [Address 00FC “0” can be set by software, but “1” cannot be set. Interrupt Request Register Interrupt request register 2 (IREQ2) [Address 00FD B INT1 external interrupt 0 request bit (IN1R) Data slicer interrupt ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Interrupt Control Register A-D conversion • INT3 external 7 Nothing is assigned. This bit is a write disable Interrupt Control Register Rev.1.01 2003.07.16 page 154 of 170 Interrupt control register 1 (ICON1) [Address 00FE Name Functions 0 : Interrupt disabled Timer 1 interrupt enable bit (TM1E) ...
Page 155
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP PWM Mode Register PWM mode register 1 (PN) [Address 020A Nothing is assigned. These bits are write disable bits PWM Mode Register Rev.1.01 2003.07.16 page 155 of 170 Functions Name 0 : Count source supply PWM counts source 1 : Count source stop selection bit (PN0) Nothing is assigned ...
Page 156
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP ROM Correction Enable Register Rev.1.01 2003.07.16 page 156 of 170 ROM correction enable register (RCR) [Address 0210 B Name Functions 0 Vector 1 enable bit (RCR0) 0: Disabled 1: Enabled 1 Vector 2 enable bit (RCR1) 0: Disabled 1: Enabled 2, 3 Fix these bits to “0.” ...
Page 157
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Transfer direction 5 selection bit (SM5 “ ” Rev.1.01 2003.07.16 page 157 of 170 f(X )/ f(X )/ f(X )/ f(X )/ External clock 1: Internal clock pin pin 2 IN Address 0213 ] After reset )/8 CIN )/16 CIN )/32 CIN )/64 CIN — ...
Page 158
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP OSD Control Register Note: When setting bit 1 of the OSD port control register to “1,” the value which is Rev.1.01 2003.07.16 page 158 of 170 OSD control register 2 (OC2) [Address 0215 ] 16 B Name Functions Display layer b1 b0 Layer 1 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Rev.1.01 2003.07.16 page 159 of 170 Name OSC1 oscillating mode b2 b1 selection bits (CS1, CS2 • “ ” 7 Test bit (See note “ 1 ” “ 0 ” “ 1 ” Functions 0 H input polarity 0 : Positive polarity input SYNC switch bit (PC0) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Raster Color Register OSD Control Register Rev.1.01 2003.07.16 page 160 of 170 Raster color register (RC) [Address 0218 ] 16 B Name Functions Raster color R control output (See note) bits (RC0, RC1 2 Raster color G control output (See note) bits ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Top Border Control Register Top border control register 1 (TB1) [Address 021C B 0 Control bits of to top border 7 (TB10 to TB17) Notes 1: Do not set “00 Bottom Border Control Register Bottom border control register 1 (BB1) [Address 021D Notes 1: Set values fit for the following condition: Rev ...
Page 162
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Top Border Control Register Top border control register 2 (TB2) [Address 021E B 0, Control bits of 1 top border (TB20 ,TB21 Notes 1: Do not set “00 Bottom Border Control Register Bottom border control register 2 (BB2) [Address 021F Control bits of ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Vertical Position Register Vertical position register 1i (VP1i 16) [Addresses 0220 B 0 Control bits of to vertical display 7 start positions (VP1i0 to VP1i7) (See note 1) Notes 1: Do not “00 Vertical Position Register Vertical position register 2i (VP2i 16) [Addresses 0230 B 0, Control bits of ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Color Pallet Register Rev.1.01 2003.07.16 page 164 of 170 Addresses 0241 Color pallet register i (CRi 9to15) [Addresses 0241 B Name Functions signal output control output (See note) bits (CRi0, CRi1 1 2 signal output control output (See note) bits (CRi2, CRi3) ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Left Border Control Register Left Border Control Register Rev.1.01 2003.07.16 page 165 of 170 Left border control register 1 (LB1) [Address 0250 B Name Functions 0 Left border position (low-order 8 bits) Control bits left border OSC 1 (LB10 to LB17) (setting value of low-order 3 bits of LB2 16 ...
Page 166
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Right Border Control Register Right Border Control Register Rev.1.01 2003.07.16 page 166 of 170 Right border control register 1 (RB1) [Address 0252 B Name Functions Control bits of Right border position (low-order 8 bits) 0 right border T to OSC (RB10 to RB17) (setting value of low-order 3 bits of RB2 16 ...
Page 167
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP SPRITE Vertical Position Register SPRITE Vertical Position Register Rev.1.01 2003.07.16 page 167 of 170 SPRITE vertical position register 1 (VS1) [Address 0254 B Name Functions Vertical display start position (low-order 8 bits) 0 Vertical display TH start position 1 (setting value of low-order 2 bits of VS2 16 2 ...
Page 168
... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP SPRITE Horizontal Position Register SPRITE horizontal position register 1 (HS1) [Address 0256 B 0 Horizontal display to start position 7 control bits of SPRITE OSD (HS10 toHS17) Notes 1: Do not set HS1 < “30 SPRITE Horizontal Position Register SPRITE horizontal position register 2 (HS2) [Address 0257 ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP SPRITE OSD Control Register Dot size selection 6, 7 Notes Pre-devided clock period for OSD Rev.1.01 2003.07.16 page 169 of 170 SPRITE OSD control register (SC) [Address 0258 B Name Functions 0 SPRITE OSD 0: Stopped control bit 1: Operating (SC0) Pre-divide ratio ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP 19. PACKAGE OUTLINE 52P4B MMP EIAJ Package Code JEDEC Code SDIP52-P-600-1.78 – SEATING PLANE Rev.1.01 2003.07.16 page 170 of 170 Weight(g) Lead Material 5.1 Alloy 42/Cu Alloy Plastic 52pin 600mil SDIP Dimension in Millimeters Symbol Min Nom Max A – ...
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... M37281MAH–XXXSP,M37281MFH–XXXSP,M37281MKH–XXXSP, M37281EKSP Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. ...
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... REVISION DESCRIPTION LIST Rev. No. 1.00 First Edition 1.01 P128 16. PROM PROGRAMMING METHOD Name of Programming Adapter PCA7401 is changed to PCA7400. M37281MAH–XXXSP,M37281MFH–XXXSP M37281MKH–XXXSP,M37281EKSP(Rev.1.0) Data Sheet Revision Description (1/1) Rev. date 0111 0307 ...