STV8258DSX STMicroelectronics, STV8258DSX Datasheet
STV8258DSX
Specifications of STV8258DSX
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STV8258DSX Summary of contents
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Key Features ■ Fully Automatic Multi-Standard Demodulation M/N standards ● FM mono ● BTSC (US MTS) stereo and SAP standards ● ■ Multi-Channel Capability 3 I²S digital inputs, S/PDIF (in/out) ● 5.1 analog outputs ● Dolby® Pro Logic® ● ...
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Back-end Processing and Pre-scaler DATA_0 DATA_1 DATA_2 LR_CLK S_CLK 2/157 Figure 1: STV82x8 Block Diagram (TQFP80) Audio DAC Audio Matrix STV82x8 XTALOUT XTALIN CLK_SEL ...
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STV82x8 Back-end Processing and Pre-scaler DATA_0 DATA_1 DATA_2 LR_CLK SCLK A_DATA A_LR_CLK A_S_CLK D_DATA Figure 2: STV82x8 Block Diagram (TQFP100) Audio DAC Audio Matrix XTALOUT XTALIN CLK_SEL 3/157 ...
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Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STV82x8 Chapter 5 Analog Audio Matrix (Input / Output ...
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Demodulator ....................................................................................................................... 81 12.12 Audio PreProcessing & Selection ...................................................................................... 84 12.13 Matrixing ............................................................................................................................. 89 12.14 Audio Processing ............................................................................................................... 96 12.15 Mute ................................................................................................................................. 123 12.16 Beeper .............................................................................................................................. 124 12.17 SPDIF Output Configuration ............................................................................................ 126 12.18 Headphone Configuration ................................................................................................ 126 12.19 ...
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STV82x8 17.1 TQFP80 Package ............................................................................................................ 153 17.2 TQFP100 Package .......................................................................................................... 154 Chapter 18 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . ...
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General Description 1 General Description This chip performs BTSC stereo and SAP analog TV stereo sound identification and demodulation (no specific I²C programming is required). It offers various audio processing functions such as equalization, loudness, beeper, volume, balance, and surround ...
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STV82x8 Multi-Channel Capabilities I²S data input number Analog loudspeakers output number Embedded SRS® and Dolby® algorithms Dolby® Pro Logic ® (DPLI) or Dolby® Pro Logic II® (DPLII) SRS® WOW™ (WOW) or SRS® TruSurround XT™ (XT) General Capabilities S/PDIF Pass-thru BTSC ...
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... General Description Order Code: STV82x8 (Tray) STV82x8/T (Tape & Reel) For Example: STV8258DSX/T will be delivered in Tape & Reel conditioning 10/157 Figure 3: Package Ordering Information STV82x8 ...
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STV82x8 Multi-Channel Capabilities I²S data input number Analog loudspeakers output number Embedded SRS® and Dolby® algorithms Dolby® Pro Logic ® (DPLI) or Dolby® Pro Logic II® (DPLII) SRS® WOW™ (WOW) or SRS® TruSurround XT™ (XT) General Capabilities S/PDIF Pass-thru Second ...
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General Description Order Code: STV82x8F (Tray) STV82x8F/T (Tape & Reel) For Example: STV8258FDSX/T will be delivered in Tape & Reel conditioning 12/157 Figure 4: Package Ordering Information STV82x8 ...
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STV82x8 1.1 STV82x8 Overview 1.1.1 Core Features Single audio source processing: ● — IF source and/or analog stereo input (SCART) — one digital source with a maximum of 6 synchronous channels (5.1 is obtained across three I²S) SIF input signal ...
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General Description Specific stand-by mode (loop-through) ● Control by I²C bus (two I²C addresses) ● System PLL and clock generation using either a single crystal oscillator or a differential clock ● input 1.1.2 Software Information The different software combinations are ...
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STV82x8 1.2 Typical Applications The STV82x8 is specified to enable flexible, analog and digital TV chassis design (refer to Figure 6, Figure 7 and The main considerations are: all necessary connections between devices can be provided through the TV set, ...
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General Description Figure 6: STV8248 Typical Application (Analog Virtual Sound) Tuner SCART 4 x SCART (TQFP100) (TQFP100) Left Right 1. When using VDS with ST OmniSurround or SRS TruSurround XT Figure 7: STV8258 Typical Application (Digital: Virtual ...
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STV82x8 Figure 8: STV8288 Typical Application (Digital TV: Multi-Channel and Virtual Sound) Multi-Channel Digital Decoder ® (Dolby Digital) I²S Tuner SCART (TQFP100) Left Right 1. When using VDS with ST OmniSurround or SRS TruSurround XT 2. When ...
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System Clock 2 System Clock The System Clock integrates 2 independent frequency synthesizers. The first frequency synthesizer is used by the demodulator at a frequency of 24.576 MHz. The second frequency synthesizer is used by the DSP core and can ...
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STV82x8 3 Digital Demodulator The Digital Demodulator (see decoder. All channel parameters are programmed automatically by the built-in Automatic Standard Recognition System (Autostandard) in order to find the STEREO or the SAP modes. Channel parameters can also be programmed manually ...
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Digital Demodulator must be reset by re-programming the LSB of register IRQ_STATUS while checking the detected standard status by reading registers AUTOSTD_STATUS. ITo recover out-of standard FM deviations or the Sound Carrier Frequency Offset, additional I²C controls are provided without ...
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STV82x8 4 Dedicated Digital Signal Processor (DSP) A dedicated Digital Signal Processor (DSP) takes charge of all audio processing features and the low frequency signal processing features of the demodulator. The internal 24-bit architecture will ensure a high quality signal ...
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Dedicated Digital Signal Processor (DSP) The main features depend on the path: FM Channel ● — DC Removal — Prescaling — De-emphasis ( us) — Stereo Dematrix Input SCART Channel ● — DC Removal — Prescaling Input I²S ...
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STV82x8 The following software is provided for the headphone or auxiliary output: Downmix ● SRS® TruBass™ ● ST Dynamic Bass ● Smart Volume Control (SVC) ● Bass/Treble ● Loudness ● Independent Volume for each channel (Smooth Volume Control) ● Soft ...
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Dedicated Digital Signal Processor (DSP) Figure 12: Audio Processing for Loudspeakers, Headphone, SCART and S/PDIF outputs 4.3 ST WideSurround STV82x8 offers three preset ST WideSurround Sound effects on the Loudspeakers path: Music, a concert hall effect ● Movie, for films ...
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STV82x8 normal home use. The ST WideSurround system exploits a method of phase shifting to achieve a similar result using only two speakers. It restores spatiality by adding artificial phase differences. The Surround/Pseudo-stereo mode is automatically selected by the Automatic ...
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Dedicated Digital Signal Processor (DSP) 4.6.1 Bass Management Configuration 0 In some cases, the bass management filters are available in the decoder itself, so there is no need to reproduce these filters. The output configuration shown in Figure 13: Bass ...
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STV82x8 4.6.3 Bass Management Configuration 2 Configuration 2 assumes that the left and right speakers, are full range while the center and surround speakers are smaller speakers. Also, all bass data is redirected to the left and right speakers. This ...
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Dedicated Digital Signal Processor (DSP) 4.6.4 Bass Management Configuration 3 The third configuration, shown in range, then all bass information will be directed to and reproduced by the front left and front right and both surround speakers. In order to ...
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STV82x8 4.6.5 Bass Management Configuration 4 This configuration implements the Simplified Dolby configuration. The center, left surround and right surround channels are summed and then filtered by the LPF. The composite bass information is either summed back into the left ...
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Dedicated Digital Signal Processor (DSP) is processed by an identical HRTF curve but mixed much lower amount. This HRTF processing of equal (L/R) signals was again used to virtualize information to the rear of the listener. The ...
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STV82x8 The SVC is implemented on the loudspeakers path, headphone path or on both in parallel (independent settings). Also, the SVC can be applied in six-channel mode ( SubW). 4.9 ST Dynamic Bass/ST Bass Enhancer STV82x8 offers dynamic ...
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Dedicated Digital Signal Processor (DSP) 4.12 Automatic Loudness Control As the human ear does not hear the audio frequency range the same way depending on the power of the audio source, the Loudness Control corrects this effect by sensing the ...
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STV82x8 In Independent mode, the volume for the Left and Right channels for Loudspeakers or ● Headphone is controlled independently. 100% Mute 4.14 Soft Mute Control The Digital Soft Mute is applied smoothly (20 ms for 120 dB range) to ...
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Dedicated Digital Signal Processor (DSP) A beep generator is shared only by the Loudspeakers or Headphone outputs. Therefore, in the event of simultaneous beeps when in Pulse mode, only the first beep will define the effective duration that will be ...
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STV82x8 5 Analog Audio Matrix (Input / Output) The analog part of the audio matrix can be divided into two parts: the SCART input matrix and the SCART output matrix. S1in S2in S3in S4in S5in* MONO_in The SCART input matrix ...
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I²S Interface (In / Out) 6 I²S Interface (In / Out) 6.1 I²S Inputs 6.1.1 I²S Inputs in TQFP 80 Package The STV82x8 can interface with a digital sound decoder. In this case, the digital data can be input at ...
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STV82x8 6.1.2 I²S Inputs in TQFP 100 Package An additional (auxiliary) asynchronous input is available in the TQFP100 package. An I2SD_DATA input for external delay is also available, but it must be in phase with the I²S output clocks. I2S_DATA0 ...
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I²S Interface (In / Out) . I2S_DATA0 f Output = 48 kHz S I2S_SCLK f Output * 64 S I2S_LR_CLK f Output = 48 kHz S I2S_PCM_CLK 6.2.2 I²S Outputs in TQFP 100 Package Two digital stereo outputs (I²S compatible) ...
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STV82x8 Note: The Input and Output modes for I²S are exclusive in the TQFP80 package. Figure 29: I²S Data Format: Lch = LOW, Rch = HIGH (I²S Input or Output mode) I2S_LR_CLK I2S_SCLK (= 64f ) ...
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S/PDIF Input/Output 7 S/PDIF Input/Output An S/PDIF output is available for connection with an external decoder/amplifier. An internal multiplexer allows selection of either the internal signal or the external signal connected on the S/ PDIF input (for example, the signal ...
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STV82x8 8 Power Supply Management A mixed supply voltage environment requires the following voltages: 3.3V capable inputs/outputs for digital pins; ● 1.8V digital core; ● 8V capable inputs/outputs for analog audio interfaces (capability to output 2 V ● requirements); 3.3V ...
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Additional Controls and Flags 9 Additional Controls and Flags This logic contains: the headphone detection, ● the IRQ generation, signal to be output to the MCU, ● the I²C bus expander output pin. ● 9.1 Headphone Detection For headphone, the ...
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STV82x8 10 STV82x8 Reset All STV82x8 features are controlled via the I²C bus. The STV82x8 can be "reset" ways Software via the I²C bus: This clears all synchronous logic, except for the I²C bus registers. 2. ...
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I²C Interface 11 I²C Interface 11.1 I²C Address and Protocol The STV82x8 I²C interface works in Slave mode and is fully compliant with I²C standards in Fast mode (maximum frequency of 400 kHz). Two pairs of I²C chip addresses are ...
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STV82x8 11.2 Start-up and Configuration Change Procedure Hardware Reset (by pin 43) Clock PLLs progammation (for oscillator values other than 27 MHz) (bit 2 in HOST_CMD register) Device Configuration Set-up (bit 0 in DSP_RUN register) (bit 1 in DSP_RUN register) ...
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Register List 12 Register List Note: The unused bits (defined as ‘Reserved’) in the I²C registers must be kept to zero. The system clock registers (from address 08h to 0Bh and from address 5Ah to 5Dh) do not need to ...
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STV82x8 12.1 I²C Register Map By default, all I²C registers controlled by Automatic Standard Recognition System (Autostandard) are forced to Read-only mode for the user. These registers and bits are shaded in Name Ad. Reset IC General Control CUT_ID 00h ...
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Register List Name Ad. Reset BTSC Stereo and SAP STEREO_CONF 43h 00111000 STEREO_FSM_CONF 44h 00001110 STEREO_LEVEL_H 45h 00100000 STEREO_LEVEL_L 46h 00010000 SAP_CONF 47h 00000000 SAP_LEVEL_H 48h 00100000 SAP_LEVEL_L 49h 00010000 STE_CAR_LEVEL 4Ah (00000000) STE_PLL_STATUS 4Bh (00000000) STEREO_SAP_STATUS 4Ch (00000000) PLL_P_GAIN ...
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STV82x8 12.2 Software Registers Name Addr. Reset DSP Control HOST_CMD 80h 0000 0000 IRQ_STATUS 81h 0000 0000 FW_VERSION 82h (0000 0001) ONCHIP_ALGO 83h (0000 0000) DSP_STATUS 84h 0000 0000 DSP_RUN 85h 0000 0000 I2S_IN_CONFIG 86h 1000 1110 I2S_IN_SHIFT_RIGHT 87h 0000 ...
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Register List Name Addr. Reset PRESCALE_I2S0 98h 0000 0000 PRESCALE_I2S1 99h 0000 0000 PRESCALE_I2S2 9Ah 0000 0000 PEAK_DETECTOR 9Bh 0000 0000 PEAK_L 9Ch 0(000 0000) PEAK_R 9Dh 0(000 0000) PEAK_L_R 9Eh 0(000 0000) Matrixing DOWNMIX_MODE 9Fh 0111 1111 DOWNMIX_DUAL_MOD A0h ...
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STV82x8 Name Addr. Reset TRUSRND_CONTROL B7h 0000 1000 TRUSRND_DC_ELEVATI B8h 0000 1100 ON TRUSRND_INPUT_GAIN B9h 0000 0000 TRUBASS_LS_CONTRO BAh 0000 0110 L TRUBASS_LS_LEVEL BBh 00001 1001 TRUBASS_HP_CONTRO BCh 0000 0110 L TRUBASS_HP_LEVEL BDh 0000 1001 SVC_LS_CONTROL BEh 0000 0010 SVC_LS_TIME_TH ...
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Register List Name Addr. Reset VOLUME_MODES D9h 1101 1111 LS_L_VOLUME_MSB DAh 1001 1000 LS_L_VOLUME_LSB DBh 0000 0000 LS_R_VOLUME_MSB DCh 0000 0000 LS_R_VOLUME_LSB DDh 0000 0000 LS_C_VOLUME_MSB DEh 1001 1000 LS_C_VOLUME_LSB DFh 0000 0000 LS_SUB_VOLUME_MSB E0h 1001 1000 LS_SUB_VOLUME_LSB E1h 0000 ...
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STV82x8 Name Addr. Reset DAC Control DAC_CONTROL F7h 0001 1111 DAC_SW_CHANNELS F8h 0000 0000 SPDIF_SW_CHANNELS F9h 0000 0000 AutoStandard Coefficients Settings AUTOSTD_FSM FAh 0000 0000 AUTOSTD_COEFF_CTR FBh 0000 0001 L AUTOSTD_COEFF_IND FCh 0000 0000 EX_MSB AUTOSTD_COEFF_IND FDh 0000 0000 EX_LSB ...
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Register List Automatic Standard Recognition by I²C Software. This is not required if the built-in Automatic Standard Recognition System function is used (default). Bit Name Reset BUS_EXP 0 Static control by I2C of hardware pin BUS_EXP I²2S_CO_EN ...
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STV82x8 Bit Name Reset I2S_PLL 0 Selects the i2s source for the synchronization with the synthesizer (at 48KHz only) 0: I2S_LR_CLK selected 1: I2SA_LR_CLK selected SYNC_SIGN 0 Reverse the sign of the loop - To be used in case of ...
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Register List I2S_SYNC_OFFSET Address: 06h Type: R/W Bit 7 Bit 6 Bit Name Reset I2S_SFO[7:0] 0000 I²S synchronization frequency offset (±450 ppm full scale) 0000 12.4 Clocking 1 A low-jitter PLL Clock is integrated and can be fully reprogrammed using ...
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STV82x8 FS1_DIV Address: 08h Type: R/W Bit 7 Bit 6 EN_PROG 0 Bit Name Reset EN_PROG 0 FS1 programmation enable 0: FS1 I2C registers programmation ignored by system - FS1 pre-programmed automatically by SYS-CONFIG register (normal use with standard oscillator ...
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Register List FS1_PE_L Address: 0Bh Type: R/W Bit 7 Bit 6 Bit Name Reset PE_L1[7:0] 0000 FS1 Fine Selection (LSBs) 0000 12.5 Demodulator DEMOD_CTRL Address: 0Ch Type: R/W Bit 7 Bit Bit Name Reset Bits [7:3] 00000 ...
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STV82x8 Bit Name Reset Bits [7:2] 000 Reserved. FM1_CAR 0 Channel 1 FM Carrier Detector Flag 0: Not detected 1: Detected FM1_SQ 0 Channel 1 FM Squelch Detector Flag 0: Not detected 1: Detected Note: These registers allow direct access ...
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Register List AGC_GAIN Address: 0Fh Type: R/W Bit 7 Bit 6 0 Bit Name Reset Bit 7 0 Reserved. AGC_ERR[4:0] 00000 Amplifier Gain Control This is the Gain Control value of AGC. There are 20 steps of +1.5 dB (see ...
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STV82x8 12.6 Demodulator Channel 1 CARFQ1H, CARFQ1M, CARFQ1L Address: 12h to 14h Type: R/W Bit 7 Bit 6 Bit Name Reset CARFQ1[23:16] 00101110 Channel 1 DCO Carrier Frequency (8 MSBs) CARFQ1[15:8] 11100000 Channel 1 DCO Carrier Frequency CARFQ1[7:0] 00000000 Channel ...
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Register List Bitfield FM 27 kHz FIR1C7[7:0] 1Bh ACOEFF1 Address: 1Dh Type: R/W Bit 7 Bit 6 Bit Name Reset Used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 1) ACOEFF1[7:0] 00100010 Defines the damping factor ...
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STV82x8 CRF1 Address: 1Fh Type: R Bit 7 Bit 6 Bit Name Reset CRF1[7:0] (00000000) Channel 1 Carrier Recovery Frequency Displays the instantaneous frequency offset of the Channel 1 Baseband PLL Demodulator. CETH1 Address: 20h Type: R/W Bit 7 Bit ...
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Register List Bit Name Reset SQTH1[7:0] 00111100 The squelch detector measures the level of high frequency noise (> 40 kHz) and compares it to the threshold level (SQTH). If the level is below this value, the S/N of the FM ...
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STV82x8 STEREO_CONF Address:43h Type: R/W Bit 7 Bit 6 LOCK_TH_STE[7:4] Bit Name Reset LOCK_TH_STE[ 0011 BTSC Lock Stereo Threshold 7:4] 10 Gain of Stereo PLL LOOP_GAIN[1:0] 00: Gain * 4 10: Gain (Default) 0 Pilot Frequency Selection FREQ_PIL 0: 15.625-15.734 ...
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Register List STEREO_LEVEL_H Address:45h Type: R/W Bit 7 Bit 6 Bit Name Reset 00100011 Threshold High for Stereo Detection STE_LEV_H[7:0] If carrier level is > STE_LEV_H, stereo is detected STEREO_LEVEL_L Address:46h Type: R/W Bit 7 Bit 6 Bit Name Reset ...
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STV82x8 SAP_LEVEL_H Address:48h Type: R/W Bit 7 Bit 6 Bit Name Reset Threshold high for SAP detection SAP_LEV_H[7:0] 01010000 If SAP signal level is > SAP_LEV_H, SAP is detected SAP_LEVEL_L Address:49h Type: R/W Bit 7 Bit 6 Bit Name Reset ...
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Register List Bit Name Reset Bits[7:6] 00 Reserved. LOOP_GAIN[3:0] 000 Final FSM gain at the end of the stereo search process 0 Overflow append in stereo search process OVER 1: overflow 0 Stereo PLL lock status LOCK_DET 0: no lock ...
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STV82x8 Bit Name Reset PLL_P_G[7:0] 01101100 PLL Proportional Gain PLL_I_G Address:4Eh Type: R/W Bit 7 Bit Bit Name Reset Bits [7:4] 0000 Reserved. PLL_I_G[3:0] 0011 PLL integral Gain SAP_SQ_TH Address:4Fh Type: R/W Bit 7 Bit 6 Bit ...
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Register List Bit Name Reset Source selection for output I2S_DATA0 000: LR I2S_DATA0_CTRL[ 000 001: HP_LSS 2:0] 010: LS_C and LS_SUB 011: SCART DAC Bit[4] 0 Reserved. Control of the power up of the Audio ADC ADC_POWER_UP 1 0: ADC ...
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STV82x8 SCART3_OUTPUT_CTRL Address: 58h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:4] 0000 Reserved. Mute command for the output SCART 3 SC3_MUTE 1 0: output not muted 1: output muted SC3_OUTPUT_SE Selection of the output SCART ...
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Register List 12.8 Clocking 2 FS2_DIV Address: 5Ah Type: R/W Bit 7 Bit Bit Name Reset Bit [7:6] 0 Reserved. NDIV2[1:0] 01 FS2 Input clock divider selection Bit 4 0 Reserved. SDIV2[2:0] 001 FS2 Output clock divider ...
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STV82x8 FS2_PE_L Address: 5Dh Type: R/W Bit 7 Bit 6 Bit Name Reset 0010 PE_L2[7:0] FS2 Fine Selection (LSBs) 1001 12.9 DSP Control HOST_CMD Address: 80h Type: R/W Bit 7 Bit 6 IT_IN_DSP 0 Bit Name Reset IT_IN_DSP 0 Valid ...
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Register List Bit Name Reset IRQ3 0 I2S SRC freq change detected IRQ2 0 I2S sync found IRQ IRQ1 0 I2S sync lost IRQ IRQ0 0 Auto-Standard IRQ FW_VERSION Address: 82h Type: R Bit 7 Bit 6 Bit Name Reset ...
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STV82x8 DSP_STATUS Address: 84h Type: R Bit 7 Bit Bit Name Reset Bits[7:1] 0000000 Reserved. DSP Initialization INIT_MEM 0 0: DSP is not initialized. 1: DSP is initialized. DSP_RUN Address: 85h Type: R/W Bit 7 Bit 6 ...
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Register List I2S_IN_CONFIG Address: 86h Type: R/W Bit 7 Bit 6 LOCK_MODE RESET_I2S _EN Bit Name Reset 0: Disable Lock Mode for external I2S input LOCK_MODE_EN 1 1: Enable Lock Mode for external I2S input RESET_I2S 0 Reset I2S input ...
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STV82x8 I2S_IN_MASK Address: 88h Type: R/W Bit 7 Bit Bit Name Reset Bits [7:5] 000 Reserved WORD_MASK[4:0] 11111 Define the mask to apply to 32-bit input samples. Range Note: This register has to be ...
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Register List 12.10 Automatic Standard Recognition AUTOSTD_CTRL Address: 8Ah Type: R/W Bit 7 Bit 6 MONO_SAP_C FORCE_SQ_S SINGLE_SHOT TRL_MATRIX Bit Name Reset SINGLE_SHOT Single-shot mode (To be selected whith any of the Mono/Stereo or Sap check bits Single ...
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STV82x8 Bit Name Reset Bits [7:5] 000 Reserved STEREO_TIME[2:0] Stereo Detection Time-out 000: 000 001: 010: 011: FM_TIME[1:0] FM Detection Time-out Note: The time-out default value is optimum and does not normally need ...
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Register List Bit Name Reset Bits[7] 0 Reserved. 0: Stereo Lock Not Detected LCK_DET 0 1: Stereo Lock Detected 0: Stereo Not Detected ST_DET 0 1: Stereo Detected 0: SAP Squelch Not Detected SAP_SQ 0 1: SAP Squelch Detected 0: ...
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STV82x8 I2S_IN_DELAY_CONFIG Address: 8Fh Type: R/W Bit 7 Bit Bit Name Reset Bits[7:6] 00 Reserved. I²S Synchronisation: SYNC 0 0: Direct Capture 1: Wait for Sync signal LRCLK_START according to LRCLK POLARITY, first data take ...
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Register List Bit Name Reset Set the prescale of the signal coming from the demodulator when STEREO is demodulated in order to optimize the signal level at DBX block input (steps of 0.02 dB): 1000 0000: BTSC_FINE_PRES 0000 ... CALE_ST[7:0] ...
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STV82x8 Bit Name Reset DEEMPHASIS_CH Select the demmphasis for demodulator second channel : 1[1:0] 00 00: No De-emphasis 01: 25 µs De-emphasis DEEMPHASIS_CH Select the demmphasis for demodulator first channel : 0[1:0] 00 00: No De-emphasis 01: 25 µs De-emphasis ...
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Register List 12.12 Audio PreProcessing & Selection PRESCALE_DEMOD_MONO Address: 94h Type: R/W Bit 7 Bit 6 PRESCALE_D EMOD_SELEC T_SAP Bit Name Reset PRESCALE_DEMO Select the prescale value to apply on channel 0 (Mono/Stereo): D_SELECT_SAP 0: Apply STEREO Prescale (95h) to ...
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STV82x8 PRESCALE_DEMOD_SAP Address: 96h Type: R/W Bit 7 Bit 6 0 Bit Name Reset Bits[7] 0 Reserved. PRESCALE_DEMO Set the prescale of the signal coming from the demodulator when SAP (channel 0): D_SAP[6:0] 101 0000: ... 000 0000 000 0000: ...
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Register List Bit Name Reset Bits[7] 0 Reserved. PRESCALE_I2S0[ Set the prescale of the signal coming from the I2S0 (SRC input or I2S0 in multichannel input 6:0] mode): 101 0000: ... 000 0000 000 0000: 000 0001: ... 011 0000: ...
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STV82x8 PEAK_DETECTOR Address: 9Bh Type: R Bit 7 Bit 6 0 PEAK_L_R_RANGE[2:0] Bit Name Reset Bits[7] 0 Reserved. PEAK_L_R_RANG Control the sensitivity of the “Left - Right” peak measurement (register 0x9E). E[2:0] The difference between Left and Right signal is ...
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Register List PEAK_R Address: 9Dh Type: R/W Bit 7 Bit 6 OVERLOAD_R Bit Name Reset OVERLOAD_R This bit is set the DSP when the Right peak detector reaches its maximum value (0x7F can be reset ...
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STV82x8 12.13 Matrixing DOWNMIX_MODE Address: 9Fh Type: R/W Bit 7 Bit 6 LT_RT_OUT_M MIX_OUT_MODE[2:0] ODE Bit Name Reset LT_RT_OUT_MOD Define to format for downmix Lt/Rt output Lt/Rt Prologic compatible mode 1: L/R stereo mode MIX_OUT_MODE[ Select output ...
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Register List Parameter Coding (bin) 011 100 101 110 111 DOWNMIX_DUAL_MODE Address: A0h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:5] 000 Reserved. DUAL_ON Select dual mode for DownMix bloc in case of dual language (in ...
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STV82x8 Bit Name Reset CENTER_FACTOR 00 00 [1:0] 01: -4.5 dB LR_UPMIX 0 0: Upmixing disabled 1: Upmixing enabled (DTS specified) NORMALIZE 1 0: Normalization disabled 1: Nnormalization enabled AUDIO_MATRIX1 Address: A2h Type: R/W Bit 7 Bit 6 ...
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Register List AUDIO_MATRIX3 Address: A4h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:6] 00 Reserved. SPDIF_OUT[1:0] 010 Select the source to output on SPDIF. See table 4. DELAY_OUT[1:0] 010 Select the source to output on DELAY. ...
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STV82x8 Bit Name Reset AUTOSTD_CTRL_ 0 If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing SPDIF (bits[2:0]) for SPDIF output channels depending on the detected standard (see table 6). 0: Manual Matrix Selection 1: Automatic Matrix ...
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Register List Bit Name Reset AUTOSTD_CTRL_ 0 If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing SCART1 (Bits[2:0]) for SCART1 output channels depending on the detected standard (see table 6). 0: Manual Matrix Selection 1: Automatic ...
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STV82x8 Bit Name Reset CM_SOURCE_SPD 000 Select the source to copy on SPDIF channel. See table 7. IF[2:0] CM_POSITION_SP 00 Select the position for the SPDIF matrix. See block diagram. DIF[1:0] CM_MATRIX_SPDI 0000 Select the matrixing for the SPDIF channels. ...
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Register List Table 16: Channel Matrix Source Selection (Continued) Parameter Coding (Bin) 110 - 111 - DEMOD_DC_LEVEL Address: AAh Type: R Bit 7 Bit 6 Bit Name Reset DEMOD_DC_LEVE (0000 Display the amount of the DC component in the signal ...
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STV82x8 AV_DELAY_TIME_LS Address: AEh Type: R/W Bit 7 Bit 6 Bit Name Reset Set the delay time for LS channel. 0000 0000: AV_DELAY_TIME_ 0000 0000 0001: LS[7:0] 0000 ... 1011 0001: Note: this value must be updated when AV_DELAY_ON = ...
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Register List Bit Name Reset 0: Reset the LFE channel PL2_LFE 0 1: Bypass the LFE channel 000: PL2_OUTPUT_DO 001: 000 WNMIX[2:0] 010: 011: 000: 001: PL2_MODES[2:0] 000 010: 011: 0: Dolby Prologic 2 is not active PL2_ACTIVE 0 1: ...
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STV82x8 Bit Name Reset Bit 7 0 Reserved. ProLogic 2 center width: 000: PL2_C_WIDTH[2:0] 000 001: 010: 011: Bit 3 0 Reserved. ProLogic 2 dimension: 000: PL2_DIMENSION [ 000 001: 2:0] 010: 011: PRO_LOGIC2_LEVEL Address: B3h Type: R/W Bit 7 ...
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Register List Bit Name Reset CENTER_NOISE 0 1: Generates noise on LS center output RIGHT_NOISE 0 1: Generates noise on LS right output LEFT_NOISE 0 1: Generates noise on LS left output 0: Noise Generation not active NOISE_ON 0 1: ...
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STV82x8 TRUSRND_CONTROL Address: B7h Type: R/W Bit 7 Bit 6 DIALOG_CLA HEADPHONE RITY_ON _ON Bit Name Reset 0: Dialog Clarity OFF DIALOG_CLARITY 1: Dialog Clarity ON 0 _ON Note: The Dialog Clarity Level is set in register 0xB8: TRUSRND_DC_ELEVATION Process ...
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Register List TRUSRND_INPUT_GAIN Address: B9h Type: R/W Bit 7 Bit 6 Bit Name Reset TRUSRND_INPUT_ 0000 Input Gain attenuation: GAIN[7:0] 0000 0000 0000: 0000 0001: ... 1111 1111: TRUBASS_LS_CONTROL Address: BAh Type: R/W Bit 7 Bit Bit ...
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STV82x8 Bit Name Reset TRUBASS_LS_LEV 0000 Define the amount of SRS TruBass effect for LS outputs: EL[7:0] 1001 0000 0000: 0000 0001: ... 1111 1111: TRUBASS_HP_CONTROL Address: BCh Type: R/W Bit 7 Bit 6 SRS_TSXT_G 0 AIN_ON Bit Name Reset ...
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Register List SVC_LS_CONTROL Address: BEh Type: R/W Bit 7 Bit Bit Name Reset Bits[7:4] 0000 Reserved. SVC_LS_INPUT[ Select input for peak detection in multichannel mode: 1:0] 00: Left/Right 00 01: Center 10: Left/Right/Center 11: Not Used SVC_LS_AMP ...
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STV82x8 Table 17: Gain (Threshold Field) Values in Manual mode (Continued) SVC_LS_GAIN Address: C0h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:6] 00 Reserved. Manual Mode Gain (dB) 00001 +3.5 00000 0 11111 -2.5 11110 -6 ...
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Register List Bit Name Reset Set “make-up” gain applied at SVC LS output: 000000: 000001: SVC_LS_GAIN[5:0] 000000 ... 101110: 101111: 110000: SVC_HP_CONTROL Address: C1h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 0000 00 Reserved. SVC_HP_AMP ...
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STV82x8 SVC_HP_GAIN Address: C3h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:6] 00 Reserved. Set “make-up” gain applied at SVC HP output: 000000: 000001: SVC_HP_GAIN[5:0] 000000 ... 101110: 101111: 110000: WIDESRND_CONTROL Address: C4h Type: R/W Bit ...
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Register List Bit Name Reset Bits[7:6] 00 Reserved. WIDESRND_BASS[ 01 Defines the bass frequency effect for ST Wide Surround Sound. Programmable values are listed in 1:0] Table 10. WIDESRND_MEDI 01 Defines the medium frequency effect for ST Wide Surround Sound ...
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STV82x8 Bit Name Reset 00: OFF 01: Low ST_VOICE[1:0] 00 10: Mid 11: High SRND_PHASE_INV Invert Right Surround phase in 2_2 or 3_2 input mode Right Surround phase not inverted 1: Right Surround phase invertedl OMNISRND_INPUT 0000: _ ...
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Register List Bit Name Reset HP_BASS_LEVEL[ ST Dynamic Bass output gain: 4:0] 00000: 00001: 00000 ... 11101: 11110: 11111: HP_BASS_FREQ[ 00: 100-Hz Cut-Off frequency 00 1:0] 01: 150-Hz Cut-Off frequency HP_DYN_BASS_O 0: ST Dynamic Bass OFF ...
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STV82x8 Bit Name Reset Bits[7:3] 00000 Reserved. HP_BT_ON 0 Bass-Treble for HP Enable 0: Bass-Treble is disabled 1: Bass-Treble is enabled LS_EQ_BT_SW 0 5-Band Equalizer or Bass-Teble for LS selection 0: 5-Band Equalizer is selected for Loudspeakers. 1: Bass-Treble is ...
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Register List LS_BASS_GAIN Address: D2h Type: R/W Bit 7 Bit 6 Bit Name Reset LS_BASS[7:0] 0000 Gain Tuning of Loudspeakers Bass Frequency 0000 Gain may be programmed within a range between +12 dB and - steps of 0.25 ...
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STV82x8 HP_TREBLE_GAIN Address: D5h Type: R/W Bit 7 Bit 6 Bit Name Reset HP_TREBLE[7:0] 0000 Gain Tuning of Headphone Treble Frequency 0000 Gain may be programmed within a range between +12 dB and - steps of 0.25 dB. ...
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Register List Bit Name Reset OCFG_NUM[2:0] 000 Select Bass Management configuration: 000: 001: 010: 011: 100: 101: 110: 111: LS_LOUDNESS Address: D7h Type: R/W Bit 7 Bit 6 0 LS_LOUD_THRESHOLD[2:0] Bit Name Reset Bit 7 0 Reserved. LS_LOUD_THRES 000 Define ...
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STV82x8 Bit Name Reset HP_LOUD_THRES 000 Define the volume threshold level since which loudness effect is applied : HOLD[2:0] 000: 001: 010: 011: HP_LOUD_GAIN_H 010 Define the amount of Treble added by loudness effect: R[2:0] 000: 001: 010: 011: HP_LOUD_ON ...
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Register List Bit Name Reset 1 Volume mode for LS output: LS_VOLUME_ 0: Independant MODE 1: Differential LS_L_VOLUME_MSB Address: DAh Type: R/W Bit 7 Bit 6 Bit Name Reset LS_L_VOLUME_M 1001 8 MSBs of the 10-bit Left Loudspeaker Volume SB[7:0] ...
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STV82x8 LS_R_VOLUME_LSB Address: DDh Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. LS_R_VOLUME_L 00 2 LSBs of the 10-bit Right Loudspeaker Volume SB[1:0] LS_C_VOLUME_MSB Address: DEh Type: R/W Bit 7 Bit 6 Bit Name ...
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Register List LS_SUB_VOLUME_MSB Address: E0h Type: R/W Bit 7 Bit 6 Bit Name Reset LS_SUB_VOLUME 1001 8 MSBs of the 10-bit Subwoofer Loudspeaker Volume _MSB[7:0] 1000 LS_SUB_VOLUME_LSB Address: E1h Type: R/W Bit 7 Bit Bit Name Reset ...
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STV82x8 LS_SL_VOLUME_LSB Address: E3h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. LS_SL_VOLUME_L 00 2 LSBs of the 10-bit Left Surround Loudspeaker Volume SB[1:0] LS_SR_VOLUME_MSB Address: E4h Type: R/W Bit 7 Bit 6 Bit ...
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Register List LS_MASTER_VOLUME_MSB Address: E6h Type: R/W Bit 7 Bit 6 Bit Name Reset LS_MASTER_ 1110 8 MSBs of the 10-bit Master Loudspeaker Volume VOLUME_MSB[7:0] 1000 LS_MASTER_VOLUME_LSB Address: E7h Type: R/W Bit 7 Bit Bit Name Reset ...
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STV82x8 HP_L_VOLUME_LSB Address: E9h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. HP_L_VOLUME_L 00 2 LSBs of the 10-bit Left Headphone Volume SB[1:0] HP_R_VOLUME_MSB Address: EAh Type: R/W Bit 7 Bit 6 Bit Name ...
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Register List AUX_VOLUME_INDEX Address: ECh Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] 000000 Reserved. AUX_VOLUME_SE 00 Select the output on which the AUX_VOLUME values will be applied: LECT[1:0] 00: No volume applied (mandatory step to ...
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STV82x8 AUX_R_VOLUME_MSB Address: EFh Type: R/W Bit 7 Bit 6 Bit Name Reset AUX_R_VOLUME_ 0000 8 MSBs of the 10-bit Right Auxiliary Volume MSB[7:0] 0000 AUX_R_VOLUME_LSB Address: F0h Type: R/W Bit 7 Bit Bit Name Reset Bits[7:2] ...
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Register List Bit Name Reset 1 Digital Soft Mute for SCART2 output: SCART2_D_MUTE 0: Soft Mute not active 1: Soft Mute active 1 Digital Soft Mute for SCART1 output: SCART1_D_MUTE 0: Soft Mute not active 1: Soft Mute active 1 ...
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STV82x8 On beeper STOP, the register 0xF2 is reset to 0. Take care to set bit[2:1] on each BEEPER_ON action. BEEPER_MODE Address: F3h Type: R/W Bit 7 Bit 6 BEEPER_DECAY[2:0] Bit Name Reset BEEPER_DECAY [ Control the decay of the ...
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Register List Bit Name Reset BEEP_VOL[4:0] 10000 Defines the Beeper volume from steps of 3 dB. 11111 11110 11101 ... 10000: -48 dB (Default) 12.17 SPDIF Output ...
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STV82x8 Bit Name Reset Select SCART2 output: 00: SCART2 not output SCART2_OUT_SE 00 01: SCART2 signal output on C/Sub DAC LECT[1:0] 10: SCART2 signal output on Srnd/HP DAC 11: not used 1: force to output the HP signal (bypass surround) ...
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Register List DAC_SW_CHANNELS Address: F8h Type: R/W Bit 7 Bit 6 C_SUB_SW Bit Name Reset Center/Sub DAC: C_SUB_SW 00 00: Left/Right channels inverted 11: Left/Right channels non inverted Surround/HP DAC: SUR_HP_SW 00 00: Left/Right channels inverted 11: Left/Right channels non ...
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STV82x8 12.20 AutoStandard Coefficients Settings AUTOSTD_COEFF_CTRL Address: FBh Type: R/W Bit 7 Bit Bit Name Reset Bits [7:2] 000000 Reserved. AUTOSTD_COEFF 01 Control the Demod filter coeff table settings _CTRL[1:0] 01: init Coeffs to ROM values 10: ...
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Register List AUTOSTD_COEFF_VALUE Address: FEh Type: R/W Bit 7 Bit 6 Bit Name Reset AUTOSTD_COEFF 0000 FIR Coefficients table value to update _VALUE[7:0] 0000 130/157 Bit 5 Bit 4 Bit 3 AUTOSTD_COEFF_VALUE[7:0] Function STV82x8 Bit 2 Bit 1 Bit 0 ...
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STV82x8 13 Pin Descriptions 13.1 TQFP 80-pin Package AP = Analog Power ● Digital Power ● Input ● Output ● Open-Drain ● Bi-Directional ● Analog ● Table 21: ...
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Pin Descriptions Table 21: TQFP80 Pin Description (Sheet Pin STV82x8 Type No. Pin Name (STV82x8) 21 VSS33_CONV AP 22 VDD33_CONV AP 23 SC3_IN_L 24 SC3_IN_R 25 SCL_FLT 26 SCR_FLT 27 LS_C 28 LS_L 29 LS_R 30 LS_SUB ...
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STV82x8 Table 21: TQFP80 Pin Description (Sheet Pin STV82x8 Type No. Pin Name (STV82x8) 52 XTALIN_CLKXTP 53 XTALOUT_CLKXTM 54 VCC18_CLK1 AP 55 GND18_CLK1 AP 56 GND18_CLK2 AP 57 VCC18_CLK2 DP 58 VSS33_IO2 DP 59 VDD33_IO2 DP 60 ...
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Pin Descriptions Table 21: TQFP80 Pin Description (Sheet Pin STV82x8 Type No. Pin Name (STV82x8) 80 SC4_IN_R 13.2 TQFP 100-pin Package AP = Analog Power ● Digital Power ● Input ● ...
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STV82x8 Table 22: TQFP100 Pin Description (Sheet Pin STV82x8 No. Pin Name GND_SA VSS33_CONV 27 VDD33_CONV 28 SC3_IN_L 29 SC3_IN_R 30 SCL_FLT 31 SCR_FLT 32 LS_C ...
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Pin Descriptions Table 22: TQFP100 Pin Description (Sheet Pin STV82x8 No. Pin Name 56 I2SO_LR_CLK 57 I2SO_SCLK 58 I2SO_DATAO 59 S/PDIF_IN 60 S/PDIF_OUT 61 VDD33_IO1 62 VSS33_IO1 63 CK_TST_CTRL 64 VSS18 65 VDD18 66 CLK_SEL 67 XTALIN_CLKXTP ...
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STV82x8 Table 22: TQFP100 Pin Description (Sheet Pin STV82x8 No. Pin Name 90 VDD18_ADC 91 VSS18_ADC 92 SIF_P 93 SIF_N 94 SIF2_P 95 GNDPW_IF 96 VCC18_IF 97 GND18_IF 98 MONO_IN 99 SC4_IN_L 100 SC4_IN_R Type Function for ...
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Application Diagrams 14 Application Diagrams Figure 31: STV82x8 TQFP80 Application Diagram 138/157 + + + + + + + + + + + + + + + + + + + + + + + + VSS33_CONV 21 VDD33_CONV 22 ...
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STV82x8 Figure 32: STV82x8 TQFP100 Application Diagram + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + VSS33_CONV ...
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Application Diagrams Figure 33: STV82x7/STV82x8 TQFP80 Compatiblity Application Diagram 140/157 + + + + + + + + + + + + + + + + + + + + + + + + 3 1 VSS33_CONV 21 VDD33_CONV 22 ...
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STV82x8 15 Input/Output Groups Pin numbers apply to SDIP package only. VCC18_IF SIF_P73 50K GND_PSUB VCC_H SC1_OUTL 1 SC1_OUTR 2 SC2_OUTL 5 SC2_OUTR 6 SC3_OUTL 18 SC3_OUTR 19 GND_PSUB VCC33_LS LS_L 25 SCR_FLT 26 150 LS_C 27 LS_L 28 LS_R ...
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Input/Output Groups VCC33_LS VREFA 11 5K4 16K8 GND33_LS VDD33_I02 59 VCC18_CLK2 57 VCC18_CLK1 54 VDD33_I01 46 VDD18 VSS GND18_CLK1 55 GND18_CLK2 56 GND_PSUB 21 70 142/157 VB G (1.2V) VB ...
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STV82x8 VDD33_I02 BUS_EXD 68 IRQ 69 VSS VDD33_I01 S/PDIF_IN 44 VSS VDD33_I02 I2S_PCM_CLK 60 I2S_LR_CLK 61 I2S_DATA0 62 I2S_DATA1 63 I2S_DATA2 64 VSS VDD33_I02 XTALIN_CLKXTP XTALOUT_CLKXTM CLK_SEL SCL SDA Input/Output Groups VCC18_CLK1 52 GND18_CLK1 500K VCC18_CLK1 53 GND18_CLK1 VDD18 51 ...
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Input/Output Groups 34 VDD18_CONV 22 VDD33_CONV VCC_NISO 20 VCC33_LS 16 VCC33_SC 7 3 VCC_H VDD18_ADC 71 76 VCC18_IF GND18_IF 77 GNDPW_IF 75 72 VSS18_ADC GND_PSUB 70 21 GND33_LS 17 4 GND_H 8 GND33_SC GND_SA 12 33 VSS18_CONV 144/157 STV82x8 ...
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STV82x8 16 Electrical Characteristics Test Conditions: T OPER MHz, default register values for synthesizer, unless otherwise specified. 16.1 Absolute Maximum Ratings Symbol Analog and Digital 1.8 V Supply Voltage V XX_18 ( CC18_CLK1 CC18_CLK2 Analog and Digital 3.3 ...
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Electrical Characteristics 16.4 Crystal Oscillator Symbol f Crystal Series Resonance Frequency (at C21 = C22 = 27 pF load capacitor) P DF/F Frequency Tolerance at 25 °C P DF/F Frequency Stability versus Temperature within a range from ...
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STV82x8 Symbol Parameter SNR Signal to Noise FM THD Total Harmonic Distortion FM SEP Stereo Channel Separation FM 16.7 SCART to SCART Analog Path Characteristics Test Conditions: Rload Symbol Parameter Analog-to-Analog STEREO and MONO R SCART Input Resistance INSCART R ...
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Electrical Characteristics 16.8 SCART and MONO IN to I²S Path Characteristics Test Conditions: Sampling Frequency = 32 kHz, Maximum MONO_IN voltage = 0.5 V Symbol Parameter THD from SCART input THD THD ADC ADC THD from MONO_IN input SNR Signal ...
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STV82x8 16.11 MUTE Characteristics Symbol Parameter MUTE DAC Mute analog DAC MUTE SCART Mute SCART 16.12 Digital I/Os Characteristics Symbol Parameter V Low Level Input Voltage IL V High Level Input Voltage IH I Input Current IN CLK_SEL Low Level ...
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Electrical Characteristics 16.13 I²C Bus Characteristics Symbol Parameter SCL V Low Level Input Voltage IL V High Level Input Voltage IH I Input Leakage Current IL f Clock Frequency SCL t Input Rise Time R t Input Fall Time F ...
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STV82x8 SDA t BUF SCL t HD,STA SDA 16.14 I²S Bus Interface I²S Bus Interface timing values shown in Symbol Parameter I²S Input V Input I²S Low Level Voltage I2S_IL V Input I²S High Level Voltage I2S_IH Z Input I²S ...
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Electrical Characteristics Symbol Parameter I²S Left Right Strobe Output f Frequency (I²S_DATA0 and I2S_OLR I²SO_DATA0,1) I²S Serial Clock Output f Frequency (I²S_DATA0 and I2S_OSCL I²SO_DATA0,1) R I²S Serial Clock Output Ratio I2S_SCL I²S Output Delay After Falling t I2S_DEL Edge ...
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STV82x8 17 Package Mechanical Data 17.1 TQFP80 Package Figure 36: 80-Pin Thin Plastic Quad Flat Package Dim. Min 0.05 A2 1.35 b 0. 0° Table ...
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Package Mechanical Data 17.2 TQFP100 Package Figure 37: 100-Pin Thin Plastic Quad Flat Package Dim. Min 0.05 A2 1.35 b 0. θ 0° 154/157 ...
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STV82x8 18 Revision History Revision Date 0.1 15 Nov. 2004 Preliminary Datasheet - First Issue. Major updates to 0.2 19 Nov. 2004 Description on page 0.3 7 Jan. 2005 Addition of TQFP100 information. Updated 1.0 23 Feb. 2005 Diagram (TQFP100) ...
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A ..................................... 19 Analog-to-Digital Conversion Audio Matrix ............................................................ 35 Analog ..................................... 20 Automatic Frequency Control ............................................ 19 Automatic Gain Control Automatic Standard Recognition System B ............................................... 21 Back-end Processing .................................................. 25 Bass Management ................................................. 31 Bass-Treble Control ................................................................. 33 Beeper ...
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... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...