ISP1161A1 Philips Semiconductors, ISP1161A1 Datasheet
ISP1161A1
Available stocks
Related parts for ISP1161A1
ISP1161A1 Summary of contents
Page 1
... USB host only, a USB device only combination of a configurable USB host and USB device. The ISP1161A1 brings high flexibility to the systems that have it built-in. For example, a system that uses an ISP1161A1 allows it not only to be connected USB hub with a USB downstream port, but also to be connected to a device that has a USB upstream port such as a USB printer, USB camera, USB keyboard or a USB mouse ...
Page 2
... Fig 1. ISP1161A1 operating as a USB device. EMBEDDED SYSTEM DSC Fig 2. ISP1161A1 operating as a stand-alone USB host. PC (host) USB cable USB I/F Fig 3. ISP1161A1 operating as both USB host and device simultaneously. 9397 750 11828 Product data EMBEDDED SYSTEM P USB cable USB I/F USB device ...
Page 3
... Philips Semiconductors 2. Features Complies with Universal Serial Bus Specification Rev. 2.0 The Host Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) The Device Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s) Combines the HC and the single chip On-chip DC complies with most USB device class specifi ...
Page 4
... ISP1161A1BM LQFP64 plastic low profile quad flat package; 64 leads; body 7 9397 750 11828 Product data USB single-chip host and device controller Rev. 02 — 25 August 2003 ISP1161A1 Version 10 1.4 mm SOT314-2 7 1.4 mm SOT414-1 © ...
Page 5
... H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17 D15 ISP1161A1 HOST/ 28 DEVICE DACK2 27 AUTOMUX HOST BUS DACK1 34 INTERFACE EOT 26 DREQ2 25 DREQ1 30 INT2 DEVICE BUS 29 INTERFACE INT1 37 D_WAKEUP 36 D_SUSPEND 32 RESET POWER-ON RESET 3.3 V ...
Page 6
... MEMORY MANAGEMENT UNIT REGISTER ACCESS Host controller sub-blocks INTEGRATED RAM MEMORY PHILIPS SIE MANAGEMENT UNIT clock recovery Device controller sub-blocks Rev. 02 — 25 August 2003 ISP1161A1 USB Interface USB STATE clock recovery PHILIPS FRAME SIE MANAGE- MENT USB bus H_DP1 PDT_LIST USB ...
Page 7
... TTL input; three-state output 4 I/O bit 4 of bidirectional data; slew-rate controlled; TTL input; three-state output 5 I/O bit 5 of bidirectional data; slew-rate controlled; TTL input; three-state output Rev. 02 — 25 August 2003 ISP1161A1 48 D_DM 47 H_PSW2 46 H_PSW1 DGND 45 44 XTAL2 ...
Page 8
... V, this pin can either be connected to 3 left unconnected. In all cases, decouple this pin to DGND DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A1 wants to start a DMA transfer; see DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A1 wants to start a DMA transfer ...
Page 9
... NDP field in the HcRhDescriptorA register; both ports will always be enabled; see (internal pull-up resistor DMA master device to inform the ISP1161A1 of end of DMA transfer; active level is programmable; see Section 10.4 digital ground ‘ ...
Page 10
... I/O bit 0 of bidirectional data; slew-rate controlled; TTL input; three-state output 64 I/O bit 1 of bidirectional data; slew-rate controlled; TTL input; three-state output Rev. 02 — 25 August 2003 ISP1161A1 , V and V . When connected to 3 hold1 hold2 is connected CC is connected to CC Table 3 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 11
... DC. 7.5 SoftConnect The connection to the USB is accomplished by bringing D (for full-speed USB devices) HIGH through a 1.5 k pull-up resistor. In the ISP1161A1 DC, the 1.5 k pull-up resistor is integrated on-chip and is not connected to V connection is established through a command sent by the external/system microcontroller. This allows the system microcontroller to complete its initialization sequence before deciding to establish connection with the USB ...
Page 12
... DC has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1161A1 the LED will blink off for 100 ms. During ‘suspend’ state the LED will remain off. ...
Page 13
... The EOT signal is an external end-of-transfer signal used to terminate the DMA transfer. Some microprocessors may not have this signal. In this case, the ISP1161A1 provides an internal EOT signal to terminate the DMA transfer as well. Setting the HcDMAConfiguration register (21H to read, A1H to write) enables the ISP1161A1 HC internal DMA counter for DMA transfer ...
Page 14
... The ISP1161A1 register structure is a command-data register pair structure. A complete register access cycle comprises a command phase followed by a data phase. The command (also known as the index of a register) points the ISP1161A1 to the next register to be accessed. A command is 8 bits long microprocessor’s 16-bit data bus, a command occupies the lower byte, with the upper byte fi ...
Page 15
... Philips Semiconductors Fig 12. 16-bit register access cycle. Most of the ISP1161A1 internal control registers are 16-bit wide. Some of the internal control registers, however, have 32-bit width. control register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor fi ...
Page 16
... Fig 15. Accessing DC control registers. 8.4 FIFO buffer RAM access by PIO mode Since the ISP1161A1 internal memory is structured as a FIFO buffer RAM, the FIFO buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal FIFO buffer RAM is similar to accessing the internal control registers in multiple data phases ...
Page 17
... The DMA interface between a microprocessor and the ISP1161A1 is shown in Figure When doing a DMA transfer, at the beginning of every burst the ISP1161A1 outputs a DMA request to the microprocessor via the DREQ pin (DREQ1 for HC, DREQ2 for DC). After receiving this signal, the microprocessor will reply with a DMA acknowledge via the DACK pin (DACK1 for HC, DACK2 for DC), and at the same time, execute the DMA transfer through the data bus ...
Page 18
... In both figures, the hardware is configured such that DREQ is active HIGH and DACK is active LOW. 8.6 Interrupts The ISP1161A1 has separate interrupt request pins for the USB HC (INT1) and the USB DC (INT2). 8.6.1 Pin configuration The interrupt output signals have four configuration modes: ...
Page 19
... INT active INT 166 ns Mode 2 edge triggered, active LOW INT active INT 166 ns Mode 3 edge triggered, active HIGH Rev. 02 — 25 August 2003 ISP1161A1 clear or disable INT clear or disable INT MGT944 Figure 20. © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 20
... The output from the 6-input OR gate is connected to a latch, which is controlled by InterruptPinEnable (bit 0 of the HcHardwareConfiguration register). In the event in which the software wishes to temporarily disable the interrupt output of the ISP1161A1 Host Controller, the following procedure should be followed: 1. Make sure that bit InterruptPinEnable in the HcHardwareConfiguration register is set to logic 1. ...
Page 21
... ACK received for an OUT token or transmitted for an IN token. 9397 750 11828 Product data USB single-chip host and device controller 82). Rev. 02 — 25 August 2003 ISP1161A1 Figure 21 shows the relationship Table 84). Default settings © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 22
... Bit INTENA in the DcMode register is a global enable/disable bit. Figure A INT2 pin INTENA = 0 INTENA = 1 (during this time, SOF asserted an interrupt event occurs. For example, SOF asserted.) Rev. 02 — 25 August 2003 ISP1161A1 LATCH INT2 LE INTENA 22 INTENA = 0 SOF asserted 004aaa198 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 23
... Figure 22): When bit INTENA is set to logic 1, pin INT2 is asserted Figure 22): If the firmware sets bit INTENA to logic 0, pin INT2 will still 13.3.6. Rev. 02 — 25 August 2003 ISP1161A1 Section 13.1.3, Section 13.1.5 and © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 24
... It is caused by the HostControllerReset field of the HcCommandStatus register (02H to read, 82H to write). 9.2 Generating USB traffic USB traffic can be generated only when the ISP1161A1 USB the USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState field of the HcControl register before generating USB traffi ...
Page 25
... To generate USB traffic, the HCD must enter the USB transaction loop. 5. Prepare PTD data in microprocessor’s system RAM The communication between the HCD and the ISP1161A1 the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic information about the commands, status, and USB data packets ...
Page 26
... HC informs HCD of the USB traffic results The USB transaction status and the feedback from the specified USB device endpoint will be put back into the ISP1161A1 HC internal FIFO buffer RAM in PTD data format. The HCD can read back the PTD data from the internal FIFO buffer RAM ...
Page 27
... Product data USB single-chip host and device controller ActualBytes[7:0] Active MaxPacketSize[7:0] Last TotalBytes[7:0] B5_5 reserved DirectionPID[1:0] FunctionAddress[6:0] reserved Rev. 02 — 25 August 2003 ISP1161A1 Toggle ActualBytes[9:8] Speed MaxPacketSize[9:8] TotalBytes[9:8] © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 28
... BufferUnderrun During an OUT, the HC could not retrieve data from the system memory fast enough to keep up with the USB data rate. Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 29
... This bit is logic 0 at power-on reset. When this feature is not used, software used for the ISP1161A1 is the same for the ISP1160 and the ISP1161. When this bit is set to logic 1 in this PTD for interrupt endpoint transfer, only one PTD USB transaction will be sent out ...
Page 30
... FIFO buffer RAM top ITL0 ISO_A ITL buffer ITL1 ISO_B control/bulk/interrupt ATL buffer ATL data not used bottom 8 + 1280 = 1440 bytes 150 1 = 1350 bytes. Rev. 02 — 25 August 2003 ISP1161A1 programmable sizes 4 kbytes MGT950 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 31
... Remark: The PTD is defined for both ATL and ITL type data transfers. For ITL, the PTD data is put into ITL buffer RAM, and the ISP1161A1 takes care of the Ping-Pong action for the ITL buffer RAM access. Fig 27. Buffer RAM data organization. ...
Page 32
... Operation and C program example Figure 29 PIO mode. The ISP1161A1 provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port is the ITLBufferPort register (40H to read, C0H to write). For the ATL buffer RAM, the access port is the ATLBufferPort register (41H to read, C1H to write) ...
Page 33
... ATLBufferPort (16-bit width) T 000H 000H 001H 001H 3FFH 7FFH ITL1 buffer RAM (8-bit width) shows the results after running this program. Rev. 02 — 25 August 2003 ISP1161A1 EOT internal EOT toggle SOF BufferStatus Pointer automatically increments by 2 ATL buffer RAM MGT951 (8-bit width) © ...
Page 34
... Set the number of bytes to be transferred HcRegWrite(wHcTransferCounter,0x50); wCount = 0x28; // Get word count outport (HcCmdPort,0x00c1); // Command for ATL buffer write 9397 750 11828 Product data USB single-chip host and device controller Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 35
... USB single-chip host and device controller HC initialized and in USBOperational state Yes Rev. 02 — 25 August 2003 ISP1161A1 Comments microprocessor must read ATL transfer completed transfer completed PTD data processed by HC OUT packets can be seen © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 36
... ITL1 buffer because ITL0 and ITL1 are Ping-Pong structured buffers. To recover from this state, a power-on reset or software reset will have to be applied. 9397 750 11828 Product data USB single-chip host and device controller Rev. 02 — 25 August 2003 ISP1161A1 Table 5). © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 37
... AT data (frame N 1) (frame N 2) (Figure 32), the ISO part is still being written while the Start of Frame Rev. 02 — 25 August 2003 ISP1161A1 (frame N 3) MGT954 (frame N 3) MGT955 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 38
... Internal pull-down resistors for downstream ports There are four internal 15 k pull-down resistors built into the ISP1161A1 for the two downstream ports: two resistors for each port. These resistors are software selectable by programming bit 12 (2_DownstreamPort15KresistorSel) of the HcHardwareConfi ...
Page 39
... Fig 34. Downstream port power management scheme. 9397 750 11828 Product data USB single-chip host and device controller ISP1161A1 D D bit 12 HcHardware Configuration internal 004aaa180 shows the ISP1161A1 downstream port power management scheme regulator 3 detect H_OCn H_PSWn Rev. 02 — 25 August 2003 ISP1161A1 V BUS USB connector 22 22 ...
Page 40
... For the internal overcurrent detection OC , H_PSWn will output a HIGH level, logic 1 trip DSon HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE bit 12 HcHardware Configuration ISP1161A1 (2 ) 004aaa182 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. . BUS to BUS of 150 138 ...
Page 41
... H_PSWn 22 H_DMn 22 H_DPn bit Figure 23 for the HC’s flow of USB state changes. Rev. 02 — 25 August 2003 ISP1161A1 HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE HcHardware Configuration ISP1161A1 004aaa183 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 42
... The ISP1161A1 suspend and resume clock scheme is shown in Figure Remark: The ISP1161A1 can only be put into a fully suspended state only after both the HC and the DC go into the suspend state. At this point, the crystal can be turned off and the internal regulator can be put into power-down mode. ...
Page 43
... Philips Semiconductors Wake-up by pin CS (software wake-up): external microprocessor issues a chip select signal through pin CS. This method of access to the ISP1161A1 internal registers is a software wake-up. Wake-up by USB devices: root hub port issues a resume signal to the HC through the USB bus, switching the HC from the USBSuspend state to the USBResume state. This will also set bit ResumeDetected of the HcInterruptStatus register (03H to read, 83H to write) ...
Page 44
... HC Operational registers (32 bits). These operational registers are made compatible to OpenHCI (Host Controller Interface) Operational registers. This allows the OpenHCI HCD to be easily ported to the ISP1161A1. Reserved bits may be defined in future releases of this specification. To ensure interoperability, the HCD must not assume that a reserved field contains logic 0. ...
Page 45
... HCI specification that is implemented by this HC. For example, a value of 11H corresponds to version 1.1. All HC implementations that are compliant with this specification will have a value of 10H. Rev. 02 — 25 August 2003 ISP1161A1 Functionality HC Miscellaneous registers HC Buffer RAM Control registers 26 ...
Page 46
... POST. The HC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote wake-up signaling of the host system is host-bus-specific, and is not described in this specification. Rev. 02 — 25 August 2003 ISP1161A1 ...
Page 47
... The HC enters USBReset after a software reset and a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. - reserved reserved 00H reserved Rev. 02 — 25 August 2003 ISP1161A1 …continued SOC[1: © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 48
... This bit, when set, does not cause a reset to the Root Hub and no subsequent reset signaling will be asserted to its downstream ports. Section 10.1.5) and bit MasterInterruptEnable is set. The HCD can clear reserved 00H R/W Rev. 02 — 25 August 2003 ISP1161A1 HCR R/W ...
Page 49
... SF StartofFrame: At the start of each frame, this bit is set by the HC and an SOF is generated. - reserved SO SchedulingOverrun: This bit is set when the USB schedules for current frame overruns. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented. Rev. 02 — 25 August 2003 ISP1161A1 reserved ...
Page 50
... Unrecoverable Error RD 0 — ignore 1 — enable interrupt generation due to Resume Detect SF 0 — ignore 1 — enable interrupt generation due to Start of Frame - reserved SO 0 — ignore 1 — enable interrupt generation due to Scheduling Overrun Rev. 02 — 25 August 2003 ISP1161A1 R/W R/W R ...
Page 51
... A logic 0 is ignored by the HC. A logic 1 disables interrupt generation due to events specified in other bits of this register. This bit is set after a hardware or software reset. - reserved RHSC 0 — ignore 1 — disable interrupt generation due to Root Hub Status Change Rev. 02 — 25 August 2003 ISP1161A1 R/W R/W ...
Page 52
... SO 0 — ignore 1 — disable interrupt generation due to Scheduling Overrun FSMPS[14: R/W R/W R FSMPS[7:0] 00H R R/W R/W R FI[7:0] DFH R/W Rev. 02 — 25 August 2003 ISP1161A1 …continued R/W R FI[13: R/W R © Koninklijke Philips Electronics N.V. 2003. All rights reserved R R 138 ...
Page 53
... HC to reset this field to its default value. HCD may choose to restore the saved value upon completing the reset sequence reserved reserved 00H FR[7:0] 00H R Rev. 02 — 25 August 2003 ISP1161A1 FR[13: © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 54
... HcFmNumber register: bit description Symbol Description reserved FN[15:0] FrameNumber: This field is incremented when HcFmRemaining is reloaded. It rolls over to 0000H after FFFFH. When the USBOperational state is entered, this field will be incremented automatically. The HC will set bit StartofFrame in the HcInterruptStatus register. Rev. 02 — 25 August 2003 ISP1161A1 ...
Page 55
... Symbol Description reserved LST[10:0] LSThreshold: Contains a value that is compared to the FrameRemaining field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining value is calculated by the HCD, which considers transmission and set-up overhead. Default value: 1576 (628H) Rev. 02 — 25 August 2003 ISP1161A1 LST[10:8] ...
Page 56
... Access R R 9397 750 11828 Product data USB single-chip host and device controller POTPGT[7: reserved 00H R NOCP OCPM R/W R reserved Rev. 02 — 25 August 2003 ISP1161A1 NPS PSM R/W R NDP[1: © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 57
... NDP[1:0] NumberDownstreamPorts: These bits specify the number of downstream ports supported by the Root Hub. The maximum number of ports supported by the ISP1161A1 is 2. Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 58
... Product data USB single-chip host and device controller reserved N reserved N/A N/A N reserved N reserved N/A N/A N Rev. 02 — 25 August 2003 ISP1161A1 PPCM[2: R/W R/W R DR[2: R/W R/W R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 59
... Hub. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 0 — reserved Bit 1 — Device attached to Port #1 Bit 2 — Device attached to Port # reserved reserved reserved Rev. 02 — 25 August 2003 ISP1161A1 OCIC LPSC R/W R © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 60
... On write—ClearGlobalPower: In global power mode (PowerSwitchingMode = 0), this bit is written to logic 1 to turn off power to all ports (clear PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose bit PortPowerControlMask is not set. Writing a logic 0 has no effect. Rev. 02 — 25 August 2003 ISP1161A1 OCI LPS 0 ...
Page 61
... This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 — no change in PortOverCurrentIndicator 1 — PortOverCurrentIndicator has changed Rev. 02 — 25 August 2003 ISP1161A1 ...
Page 62
... CurrentConnectStatus is set. 0 — full-speed device attached 1 — low-speed device attached (write) ClearPortPower: The HCD clears bit PortPowerStatus by writing a logic 1 to this bit. Writing a logic 0 has no effect. Rev. 02 — 25 August 2003 ISP1161A1 …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 63
... ClearSuspendStatus: The HCD writes a logic 1 to initiate a resume. Writing a logic 0 has no effect. A resume is initiated only if PortSuspendStatus is set. Rev. 02 — 25 August 2003 ISP1161A1 …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 64
... ClearPortEnable: The HCD writes a logic 1 to this bit to clear bit PortEnableStatus. Writing a logic 0 has no effect. CurrentConnectStatus is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemovable[NDP]). Rev. 02 — 25 August 2003 ISP1161A1 …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 65
... OC detection. Analog input - reserved DACKMode 0 — normal operation. DACK1 is used with read and write signals 1 — reserved EOTInputPolarity 0 — active LOW 1 — active HIGH DACKInputPolarity 0 — active LOW 1 — reserved Rev. 02 — 25 August 2003 ISP1161A1 AnalogOC reserved DACKMode Enable R/W R/W R/W ...
Page 66
... BurstLen[1:0] 00 — single-cycle burst DMA 01 — 4-cycle burst DMA 10 — 8-cycle burst DMA 11 — reserved DMAEnable 0 — DMA is terminated 1 — DMA is enabled. This bit will be reset to zero when DMA transfer is completed. - reserved Rev. 02 — 25 August 2003 ISP1161A1 …continued DMA ITL_ATL_ DMARead ...
Page 67
... Counter value 00H R Counter value 00H R/W HcTransferCounter register: bit description Symbol Description Counter The number of data bytes to be read to or written from RAM. value Rev. 02 — 25 August 2003 ISP1161A1 …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 68
... HC requires the Operational register to be updated) - reserved AllEOT 0 — no event Interrupt 1 — implies that data transfer has been completed via PIO transfer or DMA transfer. Occurrence of internal or external EOT will set this bit. Rev. 02 — 25 August 2003 ISP1161A1 AllEOT ATLInt SOFITLInt ...
Page 69
... HC OPR reserved Suspended Interrupt Enable Enable R/W R/W R/W Hc PInterruptEnable register: bit description Symbol Description - reserved ClkReady 0 — power-up value 1 — enables Clkready interrupt Rev. 02 — 25 August 2003 ISP1161A1 …continued Section 9. EOT ATL SOF Interrupt Interrupt Interrupt Enable Enable Enable R/W ...
Page 70
... HC miscellaneous registers 10.5.1 HcChipID register (R: 27H) Read this register to get the ID of the ISP1161A1 silicon chip. The higher byte stands for the product name (here 61H stands for the ISP1161A1). The lower byte indicates the revision number of the product including engineering samples. ...
Page 71
... Reset[7:0] 00H W HcSoftwareReset register: bit description Symbol Description Reset[15:0] Writing a reset value of F6H will cause the HC to reset all the registers except its buffer memory. Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 72
... ITLBufferLength[15:8] 00H R ITLBufferLength[7:0] 00H R/W HcITLBufferLength register: bit description Symbol Description ITLBufferLength[15:0] Assign ITL buffer length ATLBufferLength[15:8] 00H R/W Rev. 02 — 25 August 2003 ISP1161A1 1000H bytes. For example © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 73
... Buffer read by HC ATLBuffer 0 — ATL Buffer is empty Full 1 — ATL Buffer is full ITL1Buffer 0 — 1TL1 Buffer is empty Full 1 — 1TL1 Buffer is full ITL0Buffer 0 — ITL0 Buffer is empty Full 1 — ITL0 Buffer is full Rev. 02 — 25 August 2003 ISP1161A1 ATLBuffer ITL1Buffer ITL0Buffer Full ...
Page 74
... The number of bytes for ITL0 data to be read back by the microprocessor RdITL1BufferLength[15:8] 00H RdITL1BufferLength[7:0] 00H R HcReadBackITL1Length register: bit description Symbol Description RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by the microprocessor. Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 75
... USB single-chip host and device controller DataWord[15:8] 00H R DataWord[7:0] 00H R/W HcITLBufferPort register: bit description Symbol Description DataWord[15:0] read/write ITL buffer RAM’s two data bytes DataWord[15:8] 00H R/W Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 76
... Product data USB single-chip host and device controller DataWord[7:0] 00H R/W HcATLBufferPort register: bit description Symbol Description DataWord[15:0] read/write ATL buffer RAM’s two data bytes. Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 77
... DC data transfer operation The following session explains how the ISP1161A1 handles an IN data transfer and an OUT data transfer. In the Device mode, the ISP1161A1 acts as a USB device data transfer means transfer from the ISP1161A1 to an external USB Host (through the upstream port) and an OUT transfer means transfer from external USB Host to the ISP1161A1 ...
Page 78
... When all data are read, the DREQ2 line will be de-asserted and the buffer is cleared (which means that it can be overwritten when a new packet comes in). 9397 750 11828 Product data USB single-chip host and device controller Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 79
... The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] The data flow direction is determined by bit EPDIR in the DcEndpointConfiguration register; see host (ISP1161A1 transmits); OUT: output from the USB host (ISP1161A1 receives). 11.3.3 Endpoint FIFO size The size of the FIFO determines the maximum packet size that the hardware can support for a given endpoint ...
Page 80
... OUT (64-byte fixed) 1023 double-buffered 1023-byte isochronous endpoint 16 16-byte interrupt OUT 16 16-byte interrupt IN 64 double-buffered 64-byte bulk OUT 64 double-buffered 64-byte bulk IN Rev. 02 — 25 August 2003 ISP1161A1 Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes 320 bytes ...
Page 81
... IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or via the USB bus, the ISP1161A1’s DC disables all endpoints and clears all ECRs, except for the control endpoint which is fixed and always enabled. Endpoint initialization can be done at any time ...
Page 82
... All signals connected to the ISP1161A1’s DC must enter appropriate states b. All input pins of the ISP1161A1’s DC must have a CMOS logic 0 or logic the interrupt service routine, the firmware must check the current status of the USB bus. When bit BUSTATUS in the DcInterrupt register is logic 0, the USB bus has left ‘ ...
Page 83
... Input pins of the ISP1161A1’s DC are pulled to ground via the pin buffers. Outputs are made three-state to prevent current flowing in the application. Bi-directional pins are made three-state and must be pulled to ground externally by the application. The power supply of external pull-ups must also be removed to reduce power consumption ...
Page 84
... DcInterruptEnable register is set. 3. Maximum 15 ms after starting the wake-up sequence, the ISP1161A1’s DC resumes its normal functionality case of a remote wake-up, the ISP1161A1’s DC drives a K-state on the USB bus for 10 ms. 5. Following the de-assertion of output D_SUSPEND, the application restores itself and other system components to normal operating mode. ...
Page 85
... LOW level of input CS PWROFF selects powered-off mode during ‘suspend’ state all sending data AA37H unlocks the internal registers for writing after a ‘resume’ Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 86
... I/O. The ISP1161A1’s DC supports DMA transfer for all 14 configurable endpoints (see Table operation of the ISP1161A1’s DC can be interleaved with normal I/O mode access to other endpoints. The following features are supported: • ...
Page 87
... It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of the ISP1161A1’ 8237 compatible DMA mode is given in The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge) ...
Page 88
... The 8237 now sets its address lines to 1234H and activates the MEMW and IOR control signals. 6. The 8237 asserts DACK to inform the ISP1161A1’s DC that it will start a DMA transfer. 7. The ISP1161A1’s DC now places the word to be transferred on the data bus lines, because its RD signal was asserted by the 8237 ...
Page 89
... EOT the DACK-only mode, the ISP1161A1’s DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes. Fig 42. ISP1161A1’ ...
Page 90
... Philips Semiconductors DcDMACounter register: setting bit CNTREN in the DcDMAConfiguration register. The ISP1161A1 has a 16-bit DcDMACounter register, which specifies the number of bytes to be transferred. When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from the DcDMACounter register. When the internal counter completes the transfer as programmed in the DcDMACounter, an EOT condition is generated and the DMA operation stops ...
Page 91
... Philips Semiconductors 13. DC commands and registers The functions and registers of the ISP1161A1’s DC are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in A complete access consists of two phases: 1 ...
Page 92
... Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller [1] Transaction Reference write/read 1 word Section 13.1.7 on page 99 - Section 13.1.8 on page 100 - Section 13.2.1 on page 100 N 64 bytes isochronous: N 1023 bytes interrupt/bulk bytes N 64 bytes - isochronous: [6] N 1023 bytes ...
Page 93
... Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of the ISP1161A1’s DC and to perform a device reset. 13.1.1 DcEndpointConfiguration register (R/W: 30H–3FH/20H–2FH) This command is used to access the Endpoint Confi ...
Page 94
... Selects the FIFO size according to 79 DEVADR[6: R/W R/W DcAddress register: bit description Symbol Description DEVEN A logic 1 enables the device. DEVADR[6:0] This field specifies the USB device address. Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller FFOSZ[3: R/W R/W R/W Table ...
Page 95
... Philips Semiconductors 13.1.3 DcMode register (R/W: B9H/B8H) This command is used to access the ISP1161A1’s DcMode register, which consists of 1 byte (for bit allocation: see ignored. The DcMode register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt. Code (Hex): B8/B9 — ...
Page 96
... Selects DREQ2 pin signal polarity (0 = active LOW active HIGH). Bus reset value: unchanged. DAKPOL Selects DACK2 pin signal polarity (0 = active LOW). Bus reset value: unchanged. EOTPOL Selects EOT pin signal polarity (0 = active LOW active HIGH). Bus reset value: unchanged. Rev. 02 — 25 August 2003 ISP1161A1 CLKDIV[3: R/W ...
Page 97
... Figure 43. DcInterruptEnable DcInterruptEnable register register enabled disabled INT2 pin interrupt event occurs Table 85. Rev. 02 — 25 August 2003 ISP1161A1 …continued Section 8.6.3 for details. interrupt is cleared interrupt event 004aaa197 occurs Section 8.6.3. © Koninklijke Philips Electronics N.V. 2003. All rights reserved 138 ...
Page 98
... DcDMAConfiguration register (R/W: F1H/F0H) This command defines the DMA configuration of the ISP1161A1’s DC and enables/disables DMA transfers. The command accesses the DcDMAConfiguration register, which consists of 2 bytes. The bit allocation is given in will clear bit DMAEN (DMA disabled), all other bits remain unchanged. ...
Page 99
... Bus reset value: unchanged. 89. Writing to the register sets the number of bytes for a DMA transfer. Reading Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller reserved reserved ...
Page 100
... Table 90: Bit 13.1.8 Reset Device (F6H) This command resets the ISP1161A1 DC in the same way as an external hardware reset via input RESET. All registers are initialized to their ‘reset’ values. Code (Hex): F6 — reset the device Transaction — none 13.2 Data flow commands Data fl ...
Page 101
... Philips Semiconductors Remark: Reading data after a Write Endpoint Buffer command or writing data after a Read Endpoint Buffer command will cause unpredictable behavior of the ISP1161A1 DC. Code (Hex — write (control IN, endpoint 1 to 14) Code (Hex): 10 — read (control OUT, endpoint 1 to 14) Transaction — write/read maximum ( words (isochronous endpoint: N ...
Page 102
... Setup packet. SETUPT A logic 1 indicates that the buffer contains a Setup packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 02 — 25 August 2003 ISP1161A1 SETUPT CPUBUF reserved ...
Page 103
... A logic 1 indicates that the secondary endpoint buffer is full. EPFULL0 A logic 1 indicates that the primary endpoint buffer is full. DATA_PID This bit indicates the data PID of the next packet (0 = DATA PID DATA1 PID). Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller Section 11.3.6. Section 11.3.6. 3 ...
Page 104
... A logic 1 indicates that a new event occurred before the previous status was read. DATA01 This bit indicates the PID type of the last successfully received or transmitted packet (0 = DATA0 PID DATA1 PID). Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller …continued Section 11.3.6. 3 ...
Page 105
... Unlock Device (B0H) This command unlocks the ISP1161A1’s DC from write-protection mode after a ‘resume’. In ‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption by external devices during a ‘resume’. Also, the register access for reading is possible only after the ‘Unlock Device’ command is executed. ...
Page 106
... R/W R/W R SFIRL[7:0] 00H R/W Symbol Description - reserved; must be logic 0 SFIR[12:0] Scratch Information register Rev. 02 — 25 August 2003 ISP1161A1 Table 102 SFIRH[4: R/W R/W R Table 104. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 106 of 138 ...
Page 107
... SOFRH[2:0] SOF frame number (upper byte) SOFRL[7:0] SOF frame number (lower byte) Phase Bus lines Word # command D[7:0] - D[15:8] - data D[15:0] 0 107 CHIPIDH[7:0] 61H CHIPIDL[7:0] 23H R Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller SOFRH[2: Description command code (B4H) ignored frame number ...
Page 108
... A logic 1 indicates the interrupt source: control IN endpoint. EP0OUT A logic 1 indicates the interrupt source: control OUT endpoint. BUSTATUS Monitors the current USB bus status (0 = awake suspend). SP_EOT A logic 1 indicates that an EOT interrupt has occurred for a short packet. Rev. 02 — 25 August 2003 ISP1161A1 Section 8.6. ...
Page 109
... A logic 1 indicates that an ‘awake’ to ‘suspend’ change of state was detected on the USB bus. RESUME A logic 1 indicates that a ‘resume’ state was detected. RESET A logic 1 indicates that a bus reset condition was detected. Rev. 02 — 25 August 2003 ISP1161A1 …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 109 of 138 ...
Page 110
... Philips Semiconductors 14. Power supply The ISP1161A1 can operate at either 3.3 V. When using the ISP1161A1’s power supply input, only V connected to the 5 V power supply. An application with power supply input is shown in 3.3 V for its internal core. This internal 3.3 V can also be obtained from V (pin 58) to supply the 1.5 k pull-up resistor of the DC side upstream port signal D_DP. The signal D_DP is connected to the standard USB upstream port connector’ ...
Page 111
... Philips Semiconductors 15. Crystal oscillator and LazyClock The ISP1161A1 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in clock signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open. See ISP1161A1 CLKOUT XTAL2 6 MHz XTAL1 Fig 46. Oscillator circuit with external crystal. ...
Page 112
... NOLAZY controls the LazyClock signal output during ‘suspend’ state. For details about the DC’s interrupt logic, see When the ISP1161A1’s DC enters the ‘suspend’ state (by setting and clearing bit GOSUSP in the DcMode register), outputs D_SUSPEND and CLKOUT change state after approximately 2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT does not stop, but changes to the 100 kHz 50% LazyClock frequency. When resuming from ‘ ...
Page 113
... V. This is because the 5 V tolerant pads CC trip PORP shows the availability of the clock with respect to the external POR. POR EXTERNAL CLOCK Rev. 02 — 25 August 2003 ISP1161A1 PORP is 3 depends on how fast V CC shows a possible curve of drops below V CC(POR) V CC(POR) V trip t3 t4 ...
Page 114
... V tolerant. 9397 750 11828 Product data USB single-chip host and device controller Conditions CC reg(3.3) V < > < Conditions with internal regulator internal regulator bypass Rev. 02 — 25 August 2003 ISP1161A1 Min Max Unit 0.5 6.0 V 0.5 4.6 V 0.5 6 100 mA [1] 2000 2000 V ...
Page 115
... C amb typical amb typical amb typical amb typical amb typical amb = unless otherwise specified. GND amb Conditions [ Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller [1] Min Typ Max [2] 3.0 3.3 3 500 - 150 500 - Min Typ Max ...
Page 116
... Conditions V V I(D ) I(D ) range 1 3 GND pin to GND enable internal resistors SoftConnect = ON steady-state drive 1% on both H_D and H_D . Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller Min Typ Max Min Typ Max [1] 0 0.8 - 2.5 ...
Page 117
... USB single-chip host and device controller = unless otherwise specified. amb Conditions crystal oscillator running [1] crystal oscillator stopped [ pF; R amb L Conditions pF; L 10 pF; L 90 [2] [2][3] Rev. 02 — 25 August 2003 ISP1161A1 Min Typ Max 160 - - - - - - 100 - 500 1 TERM Min Typ ...
Page 118
... HIGH logic LOW stop, not active (OFF) start, active (ON) valid logic level invalid logic level high-impedance (floating, three-state) Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 118 of 138 ...
Page 119
... WR HIGH to CS HIGH WHSH t WR data set-up time WDSU t WR data hold time WDH 9397 750 11828 Product data USB single-chip host and device controller Conditions Min 5 8 300 110 143 110 136 Rev. 02 — 25 August 2003 ISP1161A1 Typ Max Unit - - ...
Page 120
... USB single-chip host and device controller t SHSL t RLRH t RHRL t RLDV data data valid valid t WHWL WDH data data valid valid Conditions Rev. 02 — 25 August 2003 ISP1161A1 t SLRL t SLWL t RHSH t WHSH RHDZ data data valid valid WDSU data data valid valid MGT969 Min Typ ...
Page 121
... Product data t RHAX t AVRL t SHDZ (1) t RLRH t SHRL t RHSH t WHAX t AVWL (1) t SHWL t WHSH t WHDZ Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller 004aaa105 004aaa106 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 121 of 138 ...
Page 122
... DACK1 D [ 15:0 ] (read 15:0 ] (write Fig 55. HC single-cycle DMA timing. 9397 750 11828 Product data USB single-chip host and device controller Conditions [ ALRL t SHAH t AHRH t RLDV t RHDZ data valid data valid t WSU t WHD Rev. 02 — 25 August 2003 ISP1161A1 Min Typ Max ...
Page 123
... Fig 56. HC burst mode DMA timing. 9397 750 11828 Product data USB single-chip host and device controller Conditions [1] 4-cycle burst mode 8-cycle burst mode 4-cycle burst mode 8-cycle burst mode t RHRL RLRH Rev. 02 — 25 August 2003 ISP1161A1 Min Typ Max 102 - - 22 ...
Page 124
... USB single-chip host and device controller DREQ1 DACK1 EOT t RLIS 0 ns DREQ1 DACK1 EOT t RLIS 0 ns Conditions ASRP Rev. 02 — 25 August 2003 ISP1161A1 004aaa109 004aaa110 Min Typ Max - - 40 180 - - 004aaa111 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Unit ns ns ...
Page 125
... Fig 61. DC single-cycle DMA write timing in DACK-only mode. 9397 750 11828 Product data USB single-chip host and device controller Conditions Min - 25 180 - - t ASRP t APRS t ASAP t APDZ t ASDV Conditions Min - 180 ASAP t ASRP t APRS t ASDV t APDZ Rev. 02 — 25 August 2003 ISP1161A1 Typ Max Unit - 004aaa112 Typ Max Unit - ...
Page 126
... DMA burst repeat interval (input IHIL RD/WR HIGH to LOW) 9397 750 11828 Product data USB single-chip host and device controller Conditions EOT on; DACK on; RD/WR LOW t RSIH t ASRP t IHAP (1) t RLIS t EOT t WLIS (3) Conditions Rev. 02 — 25 August 2003 ISP1161A1 Min Typ Max 004aaa114 ...
Page 127
... Fig 64. EOT timing in DC burst mode DMA. 9397 750 11828 Product data USB single-chip host and device controller t RSIH t ILRP t IHIL Conditions EOT on; DACK on; RD/WR LOW t ISRP t RLIS t WLIS (1) t EOT Rev. 02 — 25 August 2003 ISP1161A1 t IHAP 004aaa115 Min Typ Max ...
Page 128
... DSon (2) 470 assuming that Fig 65. Typical interface circuit to Hitachi SH-3 (SH7709) RISC processor. 9397 750 11828 Product data USB single-chip host and device controller Rev. 02 — 25 August 2003 ISP1161A1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 128 of 138 ...
Page 129
... DC/DC regulator will be bypassed best to connect all four power supply pins ( Section ISP1161A1 the flexibility to be used in an embedded system under either a 3 power supply. A typical SH7709 interface circuit is shown in 21.3 Typical software model This section shows a typical software requirement for an embedded system that incorporates the ISP1161A1 ...
Page 130
... MASS STORAGE CLASS DRIVER PRINTING CLASS DRIVER HOST STACK RISC ROM ISP1161A1 RAM LEN CONTROL Fig 66. ISP1161A1 software model for DSC application. 9397 750 11828 Product data USB single-chip host and device controller FILE TRANSFER DEVICE STACK ISP1161A1 HAL USB Downstream Digital Still Camera Rev. 02 — ...
Page 131
... USB single-chip host and device controller were determined using the circuit shown in 22 D.U. (full-speed mode). L full-speed mode only: internal 1.5 k pull-up resistor on D_DP. Rev. 02 — 25 August 2003 ISP1161A1 as listed in Figure 67. test point MGT967 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 132
... 2 scale (1) ( 0.18 10.1 10.1 12.15 12.15 0.5 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC JEITA MS-026 Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller detail X (1) ( 0.75 1.45 1.45 1 0.2 0.12 0.1 0.45 1.05 1.05 EUROPEAN ISSUE DATE ...
Page 133
... 2.5 scale (1) ( 0.20 7.1 7.1 9.15 9.15 0.4 1 0.09 6.9 6.9 8.85 8.85 REFERENCES JEDEC JEITA MS-026 Rev. 02 — 25 August 2003 ISP1161A1 detail (1) ( 0.75 0.64 0.64 0.2 0.08 0.08 0.45 0.36 0.36 EUROPEAN ISSUE DATE PROJECTION 00-01-19 03-02-20 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 134
... Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 9397 750 11828 Product data USB single-chip host and device controller 2 Rev. 02 — 25 August 2003 ISP1161A1 3 350 mm so called so called small/thin packages. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 134 of 138 ...
Page 135
... For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods . 9397 750 11828 Product data methods [1] [3] , [5] , SO, SOJ [8] Rev. 02 — 25 August 2003 ISP1161A1 USB single-chip host and device controller Soldering method Wave Reflow not suitable suitable [4] not suitable suitable suitable suitable ...
Page 136
... Section 9.4.3: rephrased the paragraph, “In all PTD’s, we have assigned device Section 16. Rev. 02 — 25 August 2003 ISP1161A1 10 C measured in the atmosphere of the reflow © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 136 of 138 ...
Page 137
... MIPS-based — trademark of MIPS Technologies, Inc. SoftConnect — trademark of Koninklijke Philips Electronics N.V. StrongARM — registered trademark of ARM Ltd. SuperH — trademark of Hitachi Ltd. Rev. 02 — 25 August 2003 ISP1161A1 Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 137 of 138 ...
Page 138
... Timing symbols . . . . . . . . . . . . . . . . . . . . . . 118 20.2 Programmed I/O timing . . . . . . . . . . . . . . . . 119 20.3 DMA timing 122 21 Application information . . . . . . . . . . . . . . . . 128 21.1 Typical interface circuit . . . . . . . . . . . . . . . . . 128 21.2 Interfacing a ISP1161A1 with a SH7709 RISC processor 129 21.3 Typical software model . . . . . . . . . . . . . . . . . 129 22 Test information 131 23 Package outline . . . . . . . . . . . . . . . . . . . . . . . 132 24 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 24 ...