ISP1161A Philips Semiconductors, ISP1161A Datasheet
ISP1161A
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ISP1161A Summary of contents
Page 1
... USB host only, a USB device only combination of a configurable USB host and USB device. ISP1161A brings high flexibility to the systems that have it built-in. For example, a system that uses an ISP1161A allows it not only to be connected USB hub with a USB downstream port, but also to be connected to a device that has a USB upstream port such as a USB printer, USB camera, USB keyboard or a USB mouse ...
Page 2
... EMBEDDED SYSTEM DSC Fig 2. ISP1161A operating as a stand-alone USB host. PC (host) USB cable USB I/F Fig 3. ISP1161A operating as both USB host and device simultaneously. 9397 750 10772 Product data Full-speed USB single-chip host and device controller EMBEDDED SYSTEM P USB cable USB I/F ...
Page 3
... Philips Semiconductors 2. Features Complies with Universal Serial Bus Specification Rev. 2.0 The Host Controller portion of the ISP1161A supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s); the Device Controller portion of the ISP1161A supports data transfer at full-speed (12 Mbit/s) Combines the HC and the single chip On-chip DC complies with most USB device class specifi ...
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... LQFP64 Plastic low profile quad flat package; 64 leads; body 1.4 mm 9397 750 10772 Product data Full-speed USB single-chip host and device controller Rev. 02 — 24 March 2003 ISP1161A Version SOT314-2 SOT414-1 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
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... H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17, 63 D15 ISP1161A HOST/ 28 DEVICE DACK2 27 AUTOMUX HOST BUS DACK1 34 INTERFACE EOT 26 DREQ2 25 DREQ1 30 INT2 DEVICE BUS 29 INTERFACE INT1 37 D_WAKEUP 36 D_SUSPEND 32 RESET POWER-ON RESET 56 3.3 V ...
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... MEMORY MANAGEMENT UNIT REGISTER ACCESS Host controller sub-blocks INTEGRATED RAM MEMORY PHILIPS SIE MANAGEMENT UNIT clock recovery Device controller sub-blocks Rev. 02 — 24 March 2003 ISP1161A USB Interface USB STATE clock recovery PHILIPS FRAME SIE MANAGE- MENT USB bus H_DP1 PDT_LIST USB ...
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... TTL input; three-state output 4 I/O bit 4 of bidirectional data; slew-rate controlled; TTL input; three-state output 5 I/O bit 5 of bidirectional data; slew-rate controlled; TTL input; three-state output Rev. 02 — 24 March 2003 ISP1161A 48 D_DM 47 H_PSW2 46 H_PSW1 DGND 45 44 XTAL2 ...
Page 8
... V, this pin can either be connected to +3 left unconnected. In all cases, decouple this pin to DGND DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A wants to start a DMA transfer; see DMA request output (programmable polarity); signals to the DMA controller that the ISP1161A wants to start a DMA transfer ...
Page 9
... NDP field in the HcRhDescriptorA Register; both ports will always be enabled; see (internal pull-up resistor DMA master device to inform the ISP1161A of end of DMA transfer; active level is programmable; see 35 - digital ground ‘suspend’ state indicator output; active HIGH ...
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... I/O bit 0 of bidirectional data; slew-rate controlled; TTL input; three-state output 64 I/O bit 1 of bidirectional data; slew-rate controlled; TTL input; three-state output Rev. 02 — 24 March 2003 ISP1161A , V and V . When connected to reg(3.3) hold1 hold2 pin is CC Table 3 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 11
... HC and the DC. 7.5 SoftConnect The connection to the USB is accomplished by bringing D (for full-speed USB devices) HIGH through a 1.5 k pull-up resistor. In the ISP1161A DC, the 1.5 k pull-up resistor is integrated on-chip and is not connected to V connection is established through a command sent by the external or system microcontroller ...
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... DC has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1161A the LED will blink off for 100 ms. During ‘suspend’ state the LED will remain off. ...
Page 13
... RAM. The EOT signal is an external end-of-transfer signal used to terminate the DMA transfer. Some microprocessors may not have this signal. In this case, the ISP1161A provides an internal EOT signal to terminate the DMA transfer as well. Setting the HcDMAConfiguration Register (21H - read, A1H - write) enables the ISP1161A HC internal DMA counter for DMA transfer ...
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... Take the example of a microprocessor attempting to read the ISP1161A’s ID. The ID is kept in the HC’s HcChipID Register (index 27H, read only). The 16-bit register access cycle is therefore: 1 ...
Page 15
... Philips Semiconductors Fig 12. 16-bit register access cycle. Most of the ISP1161A internal control registers are 16 bits wide. Some of the internal control registers have 32-bit width. register is accessed. The complete cycle of accessing a 32-bit register consists of a command phase followed by two data phases. In the two data phases, the microprocessor fi ...
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... Fig 15. Accessing DC control registers. 8.4 FIFO buffer RAM access by PIO mode Since the ISP1161A internal memory is structured as a FIFO buffer RAM, the FIFO buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal FIFO buffer RAM is similar to accessing the internal control registers in multiple data phases ...
Page 17
... DACK pin (DACK1 for HC, DACK2 for DC), and at the same time, execute the DMA transfer through the data bus. In the DMA mode, the microprocessor must issue a read or write signal to the ISP1161A pin. The ISP1161A will repeat the DMA cycles until it receives an EOT signal to terminate the DMA transfer ...
Page 18
... Fig 18. DMA transfer in burst mode. In Figure 17 HIGH and DACK is active LOW. 8.6 Interrupts The ISP1161A has separate interrupt request pins for the USB HC (INT1) and the USB DC (INT2). 8.6.1 Pin configuration The interrupt output signals have four configuration modes: Mode 0 ...
Page 19
... INT active INT 166 ns Mode 2 edge triggered, active LOW INT active INT 166 ns Mode 3 edge triggered, active HIGH Rev. 02 — 24 March 2003 ISP1161A clear or disable INT clear or disable INT MGT944 Figure 20. © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 20
... The output from the 6-input OR gate is connected to a latch, which is controlled by InterruptPinEnable (bit 0 of the HcHardwareConfiguration register). In the event in which the software wishes to temporarily disable the interrupt output of the ISP1161A Host Controller, the following procedure should be followed: 1. Make sure that bit InterruptPinEnable in the HcHardwareConfiguration register is set to logic 1. ...
Page 21
... ACK received for an OUT token or transmitted for an IN token. 9397 750 10772 Product data Full-speed USB single-chip host and device controller Figure 21 Table 82). Rev. 02 — 24 March 2003 ISP1161A shows the relationship between the Table 84). Default © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 22
... Bit INTENA in the DcMode register is a global enable/disable bit. Figure 22 INT2 pin INTENA = 0 INTENA = 1 (during this time, SOF asserted an interrupt event occurs. For example, SOF asserted.) Rev. 02 — 24 March 2003 ISP1161A LATCH INT2 C INTENA = 0 SOF asserted 004aaa198 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
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... Figure 22): When bit INTENA is set to logic 1, pin INT2 is asserted Figure 22): If the firmware sets bit INTENA to logic 0, pin INT2 will still 13.3.6. Rev. 02 — 24 March 2003 ISP1161A Section 13.1.3, Section 13.1.5 and © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 24
... It is caused by the HostControllerReset field of the HcCommandStatus Register (02H - read, 82H - write). 9.2 Generating USB traffic USB traffic can be generated only when the ISP1161A USB the USBOperational state. Therefore, the HCD must set the HostControllerFunctionalState field of the HcControl Register before generating USB traffi ...
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... To generate USB traffic, the HCD must enter the USB transaction loop. Prepare PTD data in P System RAM The communication between the HCD and the ISP1161A the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic information about the commands, status, and USB data packets. ...
Page 26
... HC informs HCD the USB traffic results The USB transaction status and the feedback from the specified USB device endpoint will be put back into the ISP1161A HC internal FIFO buffer RAM in PTD data format. The HCD can read back the PTD data from the internal FIFO buffer RAM ...
Page 27
... Product data Full-speed USB single-chip host and device controller ActualBytes[7:0] Active MaxPacketSize[7:0] Last TotalBytes[7:0] B5_5 reserved DirectionPID[1:0] FunctionAddress[6:0] reserved Rev. 02 — 24 March 2003 ISP1161A Toggle ActualBytes[9:8] Speed MaxPacketSize[9:8] TotalBytes[9:8] © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
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... BufferUnderrun During an OUT, the HC could not retrieve data from the system memory fast enough to keep up with the USB data rate. Rev. 02 — 24 March 2003 ISP1161A © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 29
... This bit is logic 0 at power-on reset. When this feature is not used, software used for ISP1161A is the same for ISP1160 and ISP1161. When this bit is set to logic 1 in this PTD for interrupt endpoint transfer, only 1 PTD USB transaction will be sent out in 1 ms. ...
Page 30
... FIFO buffer RAM top ITL0 ISO_A ITL buffer ITL1 ISO_B control/bulk/interrupt ATL buffer ATL data not used bottom 8 + 1280 = 1440 bytes 150 1 = 1350 bytes. Rev. 02 — 24 March 2003 ISP1161A programmable sizes 4 kbytes MGT950 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 31
... Figure Remark: The PTD is defined for both ATL and ITL type data transfers. For ITL, the PTD data is put into ITL buffer RAM, and the ISP1161A takes care of the Ping-Pong action for the ITL buffer RAM access. Fig 27. Buffer RAM data organization. ...
Page 32
... Operation and C program example Figure 29 mode. The ISP1161A provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port is the ITLBufferPort Register (40H - read, C0H - write). For the ATL buffer RAM, the access port is the ATLBufferPort Register (41H - read, C1H - write) ...
Page 33
... ATLBufferPort (16-bit width) T 000H 000H 001H 001H 3FFH 7FFH ITL1 buffer RAM (8-bit width) shows the results after running this program. Rev. 02 — 24 March 2003 ISP1161A EOT internal EOT toggle SOF BufferStatus Pointer automatically increments by 2 ATL buffer RAM MGT951 (8-bit width) © ...
Page 34
... Set the number of bytes to be transferred HcRegWrite(wHcTransferCounter,0x50); wCount = 0x28; // Get word count outport (HcCmdPort,0x00c1); // Command for ATL buffer write 9397 750 10772 Product data Full-speed USB single-chip host and device controller Rev. 02 — 24 March 2003 ISP1161A © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 35
... Full-speed USB single-chip host and device controller HC initialized and in USBOperational state Yes Rev. 02 — 24 March 2003 ISP1161A Comments microprocessor must read ATL transfer completed transfer completed PTD data processed by HC OUT packets can be seen © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 36
... ITL0 and ITL1 are Ping-Pong structured buffers. To recover from this state, a power-on reset or software reset will have to be applied. 9397 750 10772 Product data Full-speed USB single-chip host and device controller Rev. 02 — 24 March 2003 ISP1161A Table 5). The © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 37
... AT data (frame N 1) (frame N 2) (Figure 32), the ISO part is still being written while the Start of Frame Rev. 02 — 24 March 2003 ISP1161A (frame N 3) MGT954 (frame N 3) MGT955 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 38
... Internal pull-down resistors for downstream ports There are four internal 15 k pull-down resistors built into the ISP1161A for the two downstream ports: two resistors for each port. These resistors are software selectable by programming bit 12 (2_DownstreamPort15K resistorsel) of the HcHardwareConfi ...
Page 39
... Fig 34. Downstream port power management scheme. 9397 750 10772 Product data Full-speed USB single-chip host and device controller ISP1161A D D bit 12 HcHardware Configuration internal 004aaa088 shows the ISP1161A downstream port power management scheme regulator 3 detect H_OCn H_PSWn Rev. 02 — 24 March 2003 ISP1161A V BUS USB connector 22 22 ...
Page 40
... For the internal overcurrent detection OC , H_PSWn will output a HIGH level, logic 1 trip DSon HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE bit 12 HcHardware Configuration ISP1161A (2 ) 004aaa090 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. . BUS to BUS of 150 135 ...
Page 41
... H_PSWn 22 H_DMn 22 H_DPn bit Figure 23 for the HC’s flow of USB state changes. Rev. 02 — 24 March 2003 ISP1161A HC CORE HcHardware Configuration OC select bit Reg PSW C/L ATX SIE HcHardware Configuration ISP1161A 004aaa091 © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 42
... The ISP1161A suspend and resume clock scheme is shown in Figure Remark: The ISP1161A can only be put into a fully suspended state only after both the HC and the DC go into suspend state. At this point, the crystal can be turned off and the internal regulator can be put into power-down mode. ...
Page 43
... HC goes back into USBSuspend state. • Wake-up by pin CS (software wake-up) During the USBSuspend state, an external microprocessor issues a chip select signal through pin CS. This method of access to ISP1161A internal registers is a software wake-up. • Wake-up by USB devices For a USB bus resume, a USB device attached to the root hub port issues a resume signal to the HC through the USB bus, switching the HC from USBSuspend state to USBResume state ...
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... Section 10.6.4 on page 74 16 Section 10.6.5 on page 74 16 Section 10.6.6 on page 75 16 Section 10.6.7 on page 75 Rev. 02 — 24 March 2003 ISP1161A Functionality HC Control and Status Registers HC Frame Counter Registers HC Root Hub Registers HC DMA and Interrupt Control Registers HC Miscellaneous Registers HC Buffer RAM Control Registers © ...
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... HCI specification that is implemented by this HC. For example, a value of 11H corresponds to version 1.1. All HC implementations that are compliant with this specification will have a value of 10H reserved R/W R/W R reserved R/W R/W R/W Rev. 02 — 24 March 2003 ISP1161A ...
Page 46
... USBResume state after detecting the resume signaling from a downstream port. The HC enters USBReset after a software reset and a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. - reserved Rev. 02 — 24 March 2003 ISP1161A 10 9 RWE RWC reserved 0 0 ...
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... Product data Full-speed USB single-chip host and device controller reserved reserved reserved R/W R/W R reserved R/W R/W R/W Rev. 02 — 24 March 2003 ISP1161A SOC[1: R/W R/W R HCR R/W R/W R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 48
... MasterInterruptEnable bit is set. The HCD can reserved R/W R/W R reserved R/W R/W R reserved R/W R/W R/W Rev. 02 — 24 March 2003 ISP1161A R/W R/W R R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 49
... StartofFrame: At the start of each frame, this bit is set by the HC and an SOF is generated. - reserved SO SchedulingOverrun: This bit is set when the USB schedules for current frame overruns. A scheduling overrun will also cause the SchedulingOverrunCount of HcCommandStatus to be incremented. Rev. 02 — 24 March 2003 ISP1161A reserved ...
Page 50
... Unrecoverable Error RD 0 — ignore 1 — enable interrupt generation due to Resume Detect SF 0 — ignore 1 — enable interrupt generation due to Start of Frame - reserved SO 0 — ignore 1 — enable interrupt generation due to Scheduling Overrun Rev. 02 — 24 March 2003 ISP1161A R/W R/W R ...
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... Unrecoverable Error RD 0 — ignore 1 — disable interrupt generation due to Resume Detect SF 0 — ignore 1 — disable interrupt generation due to Start of Frame - reserved SO 0 — ignore 1 — disable interrupt generation due to Scheduling Overrun Rev. 02 — 24 March 2003 ISP1161A R/W R/W R ...
Page 52
... HC. Setting the HostControllerReset of the HcCommandStatus Register will cause the HC to reset this field to its default value. HCD may choose to restore the saved value upon completing the Reset sequence. Rev. 02 — 24 March 2003 ISP1161A ...
Page 53
... When it reaches zero reset by loading the FrameInterval value specified in the HcFmInterval register at the next bit time boundary. When entering the USBOperational state, the HC reloads it with the content of the FrameInterval part of the HcFmInterval Register and uses the updated value from the next SOF. Rev. 02 — 24 March 2003 ISP1161A ...
Page 54
... FrameNumber: This field is incremented when HcFmRemaining is reloaded. It rolls over to 0000H after FFFFH. When the USBOperational state is entered, this field will be incremented automatically. HC will set the StartofFrame bit in the HcInterruptStatus Register reserved R/W R/W R reserved R/W R/W R/W Rev. 02 — 24 March 2003 ISP1161A ...
Page 55
... Description reserved LST[10:0] LSThreshold: Contains a value that is compared to the FrameRemaining field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining value is calculated by the HCD, which considers transmission and set-up overhead. Default value: 1576 (628H) Rev. 02 — 24 March 2003 ISP1161A LST[10: R/W ...
Page 56
... HcRhDescriptorA Register: bit description Symbol Description POTPGT PowerOnToPowerGoodTime: This byte specifies the duration [7:0] HCD has to wait before accessing a powered-on port of the Root Hub. The unit of time is 2 ms. The duration is calculated as POTPGT 2 ms. - reserved Rev. 02 — 24 March 2003 ISP1161A R/W R/W R ...
Page 57
... NDP[1:0] NumberDownstreamPorts: These bits specify the number of downstream ports supported by the Root Hub. The maximum number of ports supported by ISP1161A is 2. Rev. 02 — 24 March 2003 ISP1161A …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 58
... When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PowerSwitchingMode = 0), this field is not valid. Bit 0 — reserved Bit 1 — Ganged-power mask on Port #1 Bit 2 — Ganged-power mask on Port #2 Rev. 02 — 24 March 2003 ISP1161A N/A N/A N/A ...
Page 59
... Bit 0 — reserved Bit 1 — Device attached to Port #1 Bit 2 — Device attached to Port # reserved reserved reserved reserved Rev. 02 — 24 March 2003 ISP1161A …continued OCIC LPSC R/W R OCI LPS R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 60
... PortPowerStatus). In per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing logic 0 has no effect. Rev. 02 — 24 March 2003 ISP1161A © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 61
... This bit is set when Root Hub changes the PortOverCurrentIndicator bit. The HCD writes logic 1 to clear this bit. Writing logic 0 has no effect. 0 — no change in PortOverCurrentIndicator 1 — PortOverCurrentIndicator has changed Rev. 02 — 24 March 2003 ISP1161A ...
Page 62
... ClearPortPower: The HCD clears the PortPowerStatus bit by writing logic 1 to this bit. Writing logic 0 has no effect. Rev. 02 — 24 March 2003 ISP1161A …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 63
... ClearSuspendStatus: The HCD writes logic 1 to initiate a resume. Writing logic 0 has no effect. A resume is initiated only if PortSuspendStatus is set. Rev. 02 — 24 March 2003 ISP1161A …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 64
... ClearPortEnable: The HCD writes logic 1 to this bit to clear the PortEnableStatus bit. Writing logic 0 has no effect. CurrentConnectStatus is not affected by any write. Remark: This bit always reads logic 1 when the attached device is nonremovable (DeviceRemoveable[NDP]). Rev. 02 — 24 March 2003 ISP1161A …continued © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 65
... Bit 0, InterruptPinEnable, is used as pin INT1’s master interrupt enable. This bit should be used together with the register Hc PInterruptEnable to enable pin INT1. 2. Bits 4 and 3 are fixed at logic 0 and logic 1 for the ISP1161A. Code (Hex): 20 — read Code (Hex): A0 — write Table 36: HcHardwareConfi ...
Page 66
... BurstLen[1:0] 00 — single-cycle burst DMA 01 — 4-cycle burst DMA 10 — 8-cycle burst DMA 11 — reserved DMAEnable 0 — DMA is terminated 1 — DMA is enabled This bit will be reset to zero when DMA transfer is completed - reserved Rev. 02 — 24 March 2003 ISP1161A …continued R/W R/W R/W ...
Page 67
... R/W R/W R Counter value R/W R/W R/W HcTransferCounter Register: bit description Symbol Description Counter The number of data bytes to be read to or written from RAM value Rev. 02 — 24 March 2003 ISP1161A …continued R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 68
... HC requires the Operational Register to be updated) - reserved AllEOT 0 — no event Interrupt 1 — implies that data transfer has been completed via PIO transfer or DMA transfer. Occurrence of internal or external EOT will set this bit. Rev. 02 — 24 March 2003 ISP1161A R/W R/W R/W ...
Page 69
... HC OPR reserved Suspended Interrupt Enable Enable R/W R/W R/W Hc PInterruptEnable Register: bit description Symbol Description - reserved ClkReady 0 — power-up value 1 — enables Clkready interrupt Rev. 02 — 24 March 2003 ISP1161A …continued Section 9. R/W R/W R EOT ATL SOF Interrupt Interrupt Interrupt Enable ...
Page 70
... HC miscellaneous registers 10.5.1 HcChipID Register (R: 27H) Read this register to get the ID of the ISP1161A silicon chip. The high byte stands for the product name (here 61H stands for ISP1161A). The low byte indicates the revision number of the product including engineering samples. ...
Page 71
... HcScratch Register: bit description Symbol Description Scratch[15:0] Scratch Register value Reset[15: Reset[7: HcSoftwareReset Register: bit description Symbol Description Reset[15:0] Writing a reset value of F6H will cause the HC to reset all the registers except its buffer memory. Rev. 02 — 24 March 2003 ISP1161A R/W R/W R R/W R/W R ...
Page 72
... R/W R/W R ITLBufferLength[7: R/W R/W R/W HcITLBufferLength Register: bit description Symbol Description ITLBufferLength[15:0] Assign ITL buffer length ATLBufferLength[15: R/W R/W R/W Rev. 02 — 24 March 2003 ISP1161A R/W R/W R R/W R/W R/W 1000H bytes. For example R/W R/W R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 73
... Buffer read by HC ATLBuffer 0 — ATL Buffer is empty Full 1 — ATL Buffer is full ITL1Buffer 0 — 1TL1 Buffer is empty Full 1 — 1TL1 Buffer is full ITL0Buffer 0 — ITL0 Buffer is empty Full 1 — ITL0 Buffer is full Rev. 02 — 24 March 2003 ISP1161A R/W R/W R ...
Page 74
... HcReadBackITL0Length Register: bit description Symbol Description RdITL0BufferLength[15:0] The number of bytes for ITL0 data to be read back by the microprocessor RdITL1BufferLength[15: RdITL1BufferLength[7: HcReadBackITL1Length Register: bit description Symbol Description RdITL1BufferLength[15:0] The number of bytes for ITL1 data to be read back by the microprocessor Rev. 02 — 24 March 2003 ISP1161A ...
Page 75
... R/W R DataWord[7: R/W R/W R/W HcITLBufferPort Register: bit description Symbol Description DataWord[15:0] read/write ITL buffer RAM’s two data bytes DataWord[15: R/W R/W R/W Rev. 02 — 24 March 2003 ISP1161A R/W R/W R R/W R/W R R/W R/W R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 76
... Full-speed USB single-chip host and device controller DataWord[7: R/W R/W R/W HcATLBufferPort Register: bit description Symbol Description DataWord[15:0] read/write ATL buffer RAM’s two data bytes. Rev. 02 — 24 March 2003 ISP1161A R/W R/W R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 77
... DC data transfer operation The following session explains how the ISP1161A handles an IN data transfer and an OUT data transfer. In the Device mode, ISP1161A acts as a USB device data transfer means transfer from ISP1161A to an external USB Host (through the upstream port) and an OUT transfer means transfer from external USB Host to ISP1161A ...
Page 78
... When all data are read, the DREQ2 line will be de-asserted and the buffer is cleared (which means that it can be overwritten when a new packet comes in). 9397 750 10772 Product data Full-speed USB single-chip host and device controller Rev. 02 — 24 March 2003 ISP1161A © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 79
... The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. [2] IN: input for the USB host (ISP1161A transmits); OUT: output from the USB host (ISP1161A receives). The data flow direction is determined by bit EPDIR in the DcEndpointConfiguration Register; see 11 ...
Page 80
... OUT (64 byte fixed) 1023 double-buffered 1023-byte isochronous endpoint 16 16-byte interrupt OUT 16 16-byte interrupt IN 64 double-buffered 64-byte bulk OUT 64 double-buffered 64-byte bulk IN Rev. 02 — 24 March 2003 ISP1161A Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes 320 bytes ...
Page 81
... IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or via the USB bus, the ISP1161A’s DC disables all endpoints and clears all ECRs, except for the control endpoint which is fixed and always enabled. Endpoint initialization can be done at any time ...
Page 82
... All signals connected to ISP1161A’s DC must enter appropriate states to b. All input pins of ISP1161A’s DC must have a CMOS logic 0 or logic 1 level the interrupt service routine, the firmware must check the current status of the USB bus. When bit BUSTATUS in the DcInterrupt Register is logic 0, the USB bus has left ‘ ...
Page 83
... Input pins of ISP1161A’s DC are pulled to ground via the pin buffers. Outputs are made three-state to prevent current flowing in the application. Bi-directional pins are made three-state and must be pulled to ground externally by the application. The power supply of external pull-ups must also be removed to reduce power consumption ...
Page 84
... Enable Register is set. 3. Maximum 15 ms after starting the wake-up sequence, the ISP1161A’s DC resumes its normal functionality case of a remote wake-up, ISP1161A’s DC drives a K-state on the USB bus for 10 ms. 5. Following the de-assertion of output D_SUSPEND, the application restores itself and other system components to normal operating mode. ...
Page 85
... LOW level of input CS PWROFF selects powered-off mode during ‘suspend’ state all sending data AA37H unlocks the internal registers for writing after a ‘resume’ Rev. 02 — 24 March 2003 ISP1161A © Koninklijke Philips Electronics N.V. 2003. All rights reserved 135 ...
Page 86
... I/O. ISP1161A’s DC supports DMA transfer for all 14 configurable endpoints (see Table operation of ISP1161A’s DC can be interleaved with normal I/O mode access to other endpoints. The following features are supported: • ...
Page 87
... It operates as a ‘fly-by’ DMA controller: the data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of ISP1161A’ 8237 compatible DMA mode is given in The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge) ...
Page 88
... The 8237 now sets its address lines to 1234H and activates the MEMW and IOR control signals. 6. The 8237 asserts DACK to inform ISP1161A’s DC that it will start a DMA transfer. 7. ISP1161A’s DC now places the word to be transferred on the data bus lines, because its RD signal was asserted by the 8237. ...
Page 89
... EOT DACK-only mode ISP1161A’s DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes. Fig 42. ISP1161A’ ...
Page 90
... DMAEN = 0 87): Recommended EOT usage for isochronous endpoints OUT endpoint do not use do not use preferred Rev. 02 — 24 March 2003 ISP1161A IN endpoint EOT is active transfer completes as programmed in the DcDMACounter register counter reaches zero in the middle of the buffer [1] [1] ...
Page 91
... Philips Semiconductors 13. DC commands and registers The functions and registers of ISP1161A’s DC are accessed via commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in A complete access consists of two phases: 1 ...
Page 92
... Endpoint 0 OUT Endpoint 0 IN Endpoint DcEndpointStatusImage Register endpoint 0 OUT DcEndpointStatusImage Register endpoint 0 IN DcEndpointStatusImage Register n endpoint Endpoint 0 IN and OUT DcErrorCode Register endpoint 0 OUT DcErrorCode Register endpoint 0 IN Rev. 02 — 24 March 2003 ISP1161A [1] Code (Hex) Transaction (00 bytes isochronous: N interrupt/bulk bytes (11) ...
Page 93
... Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of ISP1161A’s DC and to perform a device reset. 13.1.1 DcEndpointConfiguration Register (R/W: 30H–3FH/20H–2FH) This command is used to access the DcEndpointConfi ...
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... DcMode Register (R/W: B9H/B8H) This command is used to access the ISP1161A’s DcMode Register, which consists of 1 byte (for bit allocation: see The DcMode Register controls the DMA bus width, resume and suspend modes, interrupt activity and SoftConnect operation. It can be used to enable debug mode, where all errors and Not Acknowledge (NAK) conditions will generate an interrupt. Code (Hex): B8/B9 — ...
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... Logic 1 enables SoftConnect (see ignored if EXTPUL = 1 in the DcHardwareConfiguration Register (see Table Table NOLAZY CLKRUN R/W R/W R/W Rev. 02 — 24 March 2003 ISP1161A 2 1 DBGMOD reserved SOFTCT [1] [ R/W R/W R/W 8.6.3. Section 7.5). This bit is 83). Bus reset value: unchanged. ...
Page 96
... Selects the interrupt signalling mode on output pin INT2 (0 = level pulsed). In pulsed mode an interrupt produces an 166 ns pulse. See Section 8.6.3 Bus reset value: unchanged. INTPOL Selects INT2 pin signal polarity (0 = active LOW active HIGH). Bus reset value: unchanged. Rev. 02 — 24 March 2003 ISP1161A PWROFF INTLVL INTPOL 0 0 ...
Page 97
... Table 85 reserved R/W R/W R IEP12 IEP11 IEP10 R/W R/W R/W Rev. 02 — 24 March 2003 ISP1161A interrupt is cleared interrupt event 004aaa197 occurs Section 8.6. R/W R/W R IEP9 IEP8 IEP7 0 0 R/W R/W R/W © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 98
... DcDMAConfiguration Register (R/W: F1H/F0H) This command defines the DMA configuration of ISP1161A’s DC and enables/disables DMA transfers. The command accesses the DcDMAConfiguration Register, which consists of 2 bytes. The bit allocation is given in will clear bit DMAEN (DMA disabled), all other bits remain unchanged. ...
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... Bus reset value: unchanged. 89. Writing to the register sets the number of bytes for a DMA transfer. Reading 13 12 DMACR[15: R/W R DMACR[7: R/W R/W Rev. 02 — 24 March 2003 ISP1161A Table Section 11.2. Section 13.1.6 for more details R/W R/W R ...
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... Table 90: Bit 13.1.8 Reset Device (F6H) This command resets the ISP1161A DC in the same way as an external hardware reset via input RESET. All registers are initialized to their ‘reset’ values. Code (Hex): F6 — reset the device Transaction — none 13.2 Data flow commands Data fl ...
Page 101
... Reading the DcEndpointStatus Register will clear the interrupt bit set for the 13.2.3 EPFULL0 DATA_PID OVER WRITE Rev. 02 — 24 March 2003 ISP1161A Description command code (00H to 1FH) ignored packet length data word 1 (data byte 2, data byte 1) data word 2 (data byte 4, data byte 3) … Table 109 ...
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... Logic 1 indicates that the buffer contains a Setup packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 02 — 24 March 2003 ISP1161A Table 93). Section 11.3.6. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 102 of 135 ...
Page 103
... Setup packet. SETUPT Logic 1 indicates that the buffer contains a Setup packet. CPUBUF This bit indicates which buffer is currently selected for CPU access (0 = primary buffer secondary buffer). - reserved Rev. 02 — 24 March 2003 ISP1161A Section 11.3. SETUPT CPUBUF 0 0 ...
Page 104
... PID encoding error; bits are not the inverse of bits PID unknown; encoding is valid, but PID does not exist unexpected packet; packet is not of the expected type (token, data, or acknowledge SETUP token to a non-control endpoint token CRC error data CRC error Rev. 02 — 24 March 2003 ISP1161A Section 11.3. ERROR[3:0] ...
Page 105
... Unlock Device (B0H) This command unlocks ISP1161A’s DC from write-protection mode after a ‘resume’. In ‘suspend’ state all registers and FIFOs are write-protected to prevent data corruption by external devices during a ‘resume’. Also, the register access for reading is possible only after the ‘Unlock Device’ command is executed. ...
Page 106
... Symbol Description - reserved; must be logic 0 SFIR[12:0] Scratch Information Register reserved SOFRL[7: Symbol Description - reserved SOFRH[2:0] SOF frame number (part of upper byte) SOFRL[7:0] SOF frame number (lower byte) Rev. 02 — 24 March 2003 ISP1161A SFIRH[4: R/W R/W R R/W R/W R/W Table 104 SOFRH[2: ...
Page 107
... D[15:0] 0 107 CHIPIDH[7: CHIPIDL[7: Symbol Description CHIPIDH[7:0] chip ID code (61H) CHIPIDL[7:0] silicon version (22H) Table Section Rev. 02 — 24 March 2003 ISP1161A Description command code (B4H) ignored frame number 109. Bit BUSTATUS is used to verify the 13.1.5. Section 8.6.3. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 108
... DMA Counter reaching zero. SUSPND Logic 1 indicates that an ‘awake’ to ‘suspend’ change of state was detected on the USB bus. RESUME Logic 1 indicates that a ‘resume’ state was detected. RESET Logic 1 indicates that a bus reset condition was detected. Rev. 02 — 24 March 2003 ISP1161A ...
Page 109
... V hold1 V hold2 Fig 44. Using supply. 9397 750 10772 Product data Full-speed USB single-chip host and device controller Figure 44. ISP1161A has an internal DC/DC regulator to provide +3.3 V for , V CC Figure 45. If, however, you have board space (routing area 1 USB upstream port ...
Page 110
... Philips Semiconductors 15. Crystal oscillator and LazyClock The ISP1161A has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in signal of 6 MHz can be applied to input XTAL1, while leaving output XTAL2 open. See Figure ISP1161A CLKOUT XTAL2 6 MHz XTAL1 Fig 46. Oscillator circuit with external crystal. ...
Page 111
... NOLAZY Fig 48. Oscillator and LazyClock logic. When ISP1161A’s DC enters ‘suspend’ state (by setting and clearing bit GOSUSP in the DcMode Register), outputs D_SUSPEND and CLKOUT change state after approximately 2 ms delay. When NOLAZY = 0 the clock signal on output CLKOUT does not stop, but changes to the 100 kHz 50% LazyClock frequency. ...
Page 112
... V tolerant. 9397 750 10772 Product data Full-speed USB single-chip host and device controller Conditions pin pin V < > < Conditions with internal regulator internal regulator bypass Rev. 02 — 24 March 2003 ISP1161A Min Max Unit 0.5 6.0 V 0.5 +4.6 V 0.5 +6 100 mA [1] - 2000 V ...
Page 113
... This value is applicable to transistor input only. The value will be different if internal pull-up or pull-down resistors are used. 9397 750 10772 Product data Full-speed USB single-chip host and device controller = unless otherwise specified. amb Conditions = unless otherwise specified. GND amb Conditions [ pin to GND Rev. 02 — 24 March 2003 ISP1161A Min Typ Max [1] 3.0 3.3 3 500 - 150 500 - 22 ...
Page 114
... Full-speed USB single-chip host and device controller = unless otherwise specified. amb Conditions V V I(D ) I(D ) includes V range 1 3 GND L pin to GND enable internal resistors SoftConnect = ON steady-state drive ) both H_D and H_D . Rev. 02 — 24 March 2003 ISP1161A Min Typ Max [1] 0 0 0.8 2 0.3 2 ...
Page 115
... Product data Full-speed USB single-chip host and device controller = unless otherwise specified. amb Conditions crystal oscillator running crystal oscillator stopped [ pF; R amb L Conditions [2] [2][3] Rev. 02 — 24 March 2003 ISP1161A Min Typ Max 160 - - [ 100 - 500 1 TERM Min Typ Max ...
Page 116
... HIGH logic LOW stop, not active (OFF) start, active (ON) valid logic level invalid logic level high-impedance (floating, three-state) Rev. 02 — 24 March 2003 ISP1161A © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 116 of 135 ...
Page 117
... WR HIGH to CS HIGH WHSH t WR data set-up time WDSU t WR data hold time WDH 9397 750 10772 Product data Full-speed USB single-chip host and device controller Conditions Min 5 8 300 110 143 110 136 Rev. 02 — 24 March 2003 ISP1161A Typ Max Unit - - ...
Page 118
... Full-speed USB single-chip host and device controller t SHSL t RLRH t RHRL t RLDV data data valid valid t WHWL WDH data data valid valid Conditions Rev. 02 — 24 March 2003 ISP1161A t SLRL t SLWL t RHSH t WHSH RHDZ data data valid valid WDSU data data valid valid MGT969 Min Typ ...
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... Full-speed USB single-chip host and device controller t RHAX t AVRL t SHDZ (1) t RLRH t SHRL t RHSH t WHAX t AVWL (1) t SHWL t WHSH t WHDZ Conditions Rev. 02 — 24 March 2003 ISP1161A 004aaa105 004aaa106 Min Typ Max © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Unit ns ns ...
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... RD/WR HIGH to DACK1 HIGH SHAH t DREQ1 HIGH to DACK1 LOW SLAL 9397 750 10772 Product data Full-speed USB single-chip host and device controller …continued Conditions ALRL t SHAH t AHRH t RLDV t RHDZ data valid data valid t WSU t WHD Conditions Rev. 02 — 24 March 2003 ISP1161A Min Typ Max [ ...
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... Product data Full-speed USB single-chip host and device controller …continued Conditions 4-cycle burst mode 8-cycle burst mode 4-cycle burst mode 8-cycle burst mode t RHRL RLRH DREQ1 DACK1 EOT t RLIS 0 ns Rev. 02 — 24 March 2003 ISP1161A Min Typ Max [ 105 - - 150 - - 167 - ...
Page 122
... ASDV t data hold after DACK off APDZ 9397 750 10772 Product data Full-speed USB single-chip host and device controller DREQ1 DACK1 EOT t RLIS 0 ns Conditions ASRP Conditions Rev. 02 — 24 March 2003 ISP1161A 004aaa110 Min Typ Max - - 40 180 - - 004aaa111 Min Typ Max - - 40 ...
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... Product data Full-speed USB single-chip host and device controller t ASRP t APRS t ASAP t APDZ t ASDV Conditions Min - 180 ASAP t ASRP t APRS t ASDV t APDZ Rev. 02 — 24 March 2003 ISP1161A 004aaa112 Typ Max Unit - 004aaa113 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 124
... DMA burst repeat interval (input IHIL RD/WR HIGH to LOW) 9397 750 10772 Product data Full-speed USB single-chip host and device controller Conditions EOT on; DACK on; RD/WR LOW t RSIH t ASRP t IHAP (1) t RLIS t EOT t WLIS (3) Conditions Rev. 02 — 24 March 2003 ISP1161A Min Typ Max 004aaa114 Min ...
Page 125
... Fig 62. EOT timing in DC burst mode DMA. 9397 750 10772 Product data Full-speed USB single-chip host and device controller t RSIH t ILRP t IHIL Conditions EOT on; DACK on; RD/WR LOW t ISRP t RLIS t WLIS (1) t EOT Rev. 02 — 24 March 2003 ISP1161A t IHAP 004aaa115 Min Typ Max ...
Page 126
... and will select the Data Port of the Device Controller – and will select the Command Port of the Device Controller • The CS line is used for chip selection of ISP1161A in a certain address range of the RISC system. This signal is active LOW. 9397 750 10772 ...
Page 127
... ISP1161A. The software model for a digital still camera (DSC) is used as the example for illustration (as shown in software are required to make full use of the features in ISP1161A: the host stack and the device stack. The device stack provides API directly to the application task for device function ...
Page 128
... HOST STACK RISC ROM ISP1161A RAM LEN CONTROL Fig 64. ISP1161A software model for DSC application. 20. Test information The dynamic characteristics of the analog I/O ports (D and D Table 117 Load capacitance: Speed: Fig 65. Load impedance for D_DP and D_DM pins. 9397 750 10772 ...
Page 129
... 2 scale (1) ( 0.18 10.1 10.1 12.15 12.15 0.5 0.12 9.9 9.9 11.85 11.85 REFERENCES JEDEC EIAJ MS-026 Rev. 02 — 24 March 2003 ISP1161A detail X (1) ( 0.75 1.45 1.45 1.0 0.2 0.12 0.1 0.45 1.05 1.05 EUROPEAN ISSUE DATE PROJECTION 99-12-27 00-01-19 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 130
... 2 scale (1) ( 0.20 7.1 7.1 9.15 9.15 0.4 1.0 0.09 6.9 6.9 8.85 8.85 REFERENCES JEDEC EIAJ MS-026 Rev. 02 — 24 March 2003 ISP1161A SOT414 detail X (1) ( 0.75 0.64 0.64 7 0.2 0.08 0.08 o 0.45 0.36 0.36 0 EUROPEAN ISSUE DATE PROJECTION 99-12-27 00-01-19 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 131
... The footprint must incorporate solder thieves at the downstream end. 9397 750 10772 Product data Full-speed USB single-chip host and device controller Rev. 02 — 24 March 2003 ISP1161A 2.5mm 3 so called 3 so © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 132
... Product data Full-speed USB single-chip host and device controller methods [1] [4] , SO, SOJ Rev. 02 — 24 March 2003 ISP1161A Soldering method Wave Reflow not suitable suitable [3] not suitable suitable ...
Page 133
... RLDV Figure 50. changed the following: . RHSH Also, changed the description. SHRL SHRL RLRH Also, changed the description. SHWL SHWL WLWH Section 19.2. Section 27. Rev. 02 — 24 March 2003 ISP1161A © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 133 of 135 ...
Page 134
... MIPS-based — trademark of MIPS Technologies, Inc. SoftConnect — trademark of Koninklijke Philips Electronics N.V. StrongARM — registered trademark of ARM Ltd. SuperH — trademark of Hitachi Ltd. Rev. 02 — 24 March 2003 ISP1161A Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 134 of 135 ...
Page 135
... Timing symbols . . . . . . . . . . . . . . . . . . . . . . 116 18.2 Programmed I/O timing . . . . . . . . . . . . . . . . 117 18.3 DMA timing 119 19 Application information . . . . . . . . . . . . . . . . 126 19.1 Typical interface circuit . . . . . . . . . . . . . . . . . 126 19.2 Interfacing a ISP1161A with a SH7709 RISC processor 126 19.3 Typical software model . . . . . . . . . . . . . . . . . 127 20 Test information 128 21 Package outline . . . . . . . . . . . . . . . . . . . . . . . 129 22 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 22 ...