AMD-751AC Advanced Micro Systems, Inc., AMD-751AC Datasheet
AMD-751AC
Related parts for AMD-751AC
AMD-751AC Summary of contents
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... AMD-751 System Controller Data Sheet Publication # 21910 Rev: E Issue Date: March 2000 TM ...
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... AMD reserves the right to discontinue or make changes to its products at any time without notice. Trademarks AMD, the AMD logo, AMD Athlon, and combinations thereof, AMD-750, AMD-751, and AMD-756 are trade- marks, and AMD- registered trademark of Advanced Micro Devices, Inc. Alpha is a trademark of Digital Equipment Corporation. ...
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... Contents Revision History 1 Features 1.1 AMD Athlon™ System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Integrated Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 PCI Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 AGP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.5 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Overview 2.1 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 Processor Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.3 PCI Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.4 Accelerated Graphics Port (AGP ...
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... AMD-751™ System Controller Data Sheet 4.1.9 SDATA[63:0]# (Processor Data Channel 4.1.10 SDATAINCLK[3:0]# (System Data In Clock 4.1.11 SDATAINVAL# (System Data In Valid 4.1.12 SDATAOUTCLK[3:0]# (System Address Out 4.1.13 SYSCLK (System Clock 4.2 PCI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2.1 AD[31:0] (PCI Address/Data Bus 4.2.2 C/BE[3:0]# (PCI Command/Byte Enables ...
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... Address Mapping and Memory Organization . . . . . . . 65 5.3.4 SDRAM Interface Memory . . . . . . . . . . . . . . . . . . . . . . 67 5.3.5 Shadow RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.3.6 Synchronous DRAM (SDRAM Table of Contents Preliminary Information AMD-751™ System Controller Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... AMD-751™ System Controller Data Sheet 5.4 PCI Bus Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4.1 Memory Coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.4.2 PCI Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4.3 PCI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4.4 PCI Southbridge Signals . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.5 PCI Parity/ECC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.4.6 PCI-to-Memory/PCI-from-Memory and Other 5.4.7 PCI-to-Processor Bus Read Transactions . . . . . . . . . . . 81 5.4.8 Processor-to-PCI Bus Write Transactions . . . . . . . . . . . 81 5 ...
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... PCI Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 9.4 SDRAM Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . 190 9.5 AGP Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 9.6 AMD Athlon System Bus Timings . . . . . . . . . . . . . . . . . . . . 193 10 I/O Buffer Characteristics 10.1 I/O Buffer Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 10.2 I/O Model Application Note . . . . . . . . . . . . . . . . . . . . . . . . . 196 10.3 I/O Buffer AC and DC Characteristics . . . . . . . . . . . . . . . . . 196 ...
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... AMD-751™ System Controller Data Sheet viii Preliminary Information 21910E—March 2000 Table of Contents ...
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... Refresh Timer and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . 69 AMD-751 System Controller Clocking Scheme . . . . . . . . . . . 75 100-MHz SDRAM Detailed Timing . . . . . . . . . . . . . . . . . . . . . 76 AGP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 AGP Queues and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 AMD-751 System Controller Arbiters . . . . . . . . . . . . . . . . . . . 91 Address Remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Cache Hierarchy (Conventional Two-Level Scheme Conventional GART Scheme—Multiple Tables . . . . . . . . . . 96 Page Translation Structures Page Directory Entry (PDE) Definition . . . . . . . . . . . . . . . . . 99 Address Translation Flow Chart ...
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... AMD-751™ System Controller Data Sheet Figure 33. Figure 34. Figure 35. Figure 36. x Preliminary Information Setup, Hold, and Valid Delay Timings . . . . . . . . . . . . . . . . . 188 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Bottom Side View of Package . . . . . . . . . . . . . . . . . . . . . . . . 201 Top and Side Views of Package . . . . . . . . . . . . . . . . . . . . . . . 202 21910E—March 2000 List of Figures ...
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... SDRAM DIMM Loading Analysis . . . . . . . . . . . . . . . . . . . . . . . . 74 Key SDRAM DIMM Timing Variables . . . . . . . . . . . . . . . . . . . . 77 Summary of GART Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Mask Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 AMD-751 System Controller MSR Settings . . . . . . . . . . . . . . . 111 Configuration Port Register Summary . . . . . . . . . . . . . . . . . . 125 Function 0, Device 0 Configuration Registers . . . . . . . . . . . . 126 Function 0, Device 1 Configuration Registers . . . . . . . . . . . . 128 Memory Space Configuration Registers (BAR1 + 129 Power Management Configuration Registers (BAR2 + n) ...
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... PCLK Switching Characteristics for 33-MHz PCI Bus . . . . . . 187 PCI Interface Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 DRAM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 AGP 1x Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 AGP 2x Mode Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 AMD Athlon System Bus/AMD-751 System Controller AC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Symbol Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 492-Pin PBGA 35 35.0 mm Package Specifications . 203 Geometric Tolerances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Abbreviations ...
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... Revision History Date Rev Added cross reference to the AMD-751™ System Controller Memory Settings Application Note, order# 22835 to “SDRAM Initialization” on page 70. Added “Revision ID Nomenclature” on page 129. Changed note in Table 16, “Function 0, Device 0 Configuration Registers,” on page 126 and “ ...
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... AMD-751™ System Controller Data Sheet xiv Preliminary Information 21910E—March 2000 Revision History ...
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... Features computing platforms, delivering the ultimate performance for The AMD-750™ chipset is a highly integrated system logic so lut livers for AMD Athlon processor and other AMD Athlon system bus-compatible processors. The AMD-750 chipset consists of the AMD-751™ system controller in a 492-pin plastic ball-grid array (PBGA) package and the AMD-756™ ...
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... AMD-751™ System Controller Data Sheet 1.1 AMD Athlon™ System Bus The AMD Athlon system bus has the following features: n High-performance point-to-point system bus topology n Source-synchronous clocking for high-speed transfers n HSTL-like low-voltage swing transceiver logic signal levels n Three 200-MHz independent high-speed channels: • ...
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... Flexible row and column addressing memory-timing Programmable refresh rate CAS-before-RAS Populated banks only Chipset powerdown via SDRAM automatic refresh command Automatic refresh of availability for memory access by the processor or system Features AMD-751™ System Controller Data Sheet parameters idle slots—improves and bus 3 ...
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... AMD-751™ System Controller Data Sheet 1.3 PCI Bus Controller The PCI bus controller has the following features: n Compliance with PCI Local Bus Specification, Revision 2.2 n Supports six PCI masters n 32-bit interface, compatible with 3.3-V and 5-V PCI I/O n Synchronous PCI bus operation MHz ...
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... Power Management The power management features include the following: n Compliance support for both ACPI and Microsoft power management n The AMD-751 system controller supports the following power states: • • Chapter 1 Simultaneous issuing of requests from both the write queue and read queue ...
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... SADDOUT System Controller System Controller SERR# PREQ# PGNT# WSC# System Management, Reset, Initialize, Interrupts Figure 1. AMD-750™ Chipset System Block Diagram 6 Preliminary Information AMD Athlon™ Processor System Bus Memory Bus AMD-751™ 64-bit data + 8-bit ECC AGP Bus 32-bit ...
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... Overview The AMD-751 system controller is designed to optimize the interaction between the processor, DRAM, AGP, and the PCI bus with pipelined burst and concurrent transactions. Each bus interface includes multiple specialized FIFO buffers to enable optimum system concurrency. In the AMD-751, AMD has introduced a memory-request organizer to optimize the bandwidth of the DRAM ...
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... The BIOS must determine the type of memory installed and program the configuration registers accordingly. The AMD-751 supports the SDRAM types shown in Table 1 on page 9. It does not support x32 DRAM configurations in the 16-Mbit technology. The AMD-751 logically supports the x4 configuration, but it is not recommended with unbuffered DIMMs ...
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... Five separate PCI FIFOs containing over 300 bytes of storage are utilized to facilitate concurrency. In addition, the AMD-751 prefetches eight quadwords (one AMD Athlon processor cache line) when performing memory reads for a PCI master. Enhanced PCI bus commands, such as memory read line ...
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... AGP bus is referred to as the secondary PCI bus or A-PCI. The AMD-751 implements an AGP 1.0-compliant interface, which provides a 32-bit-wide data path operating at either 66 MHz or 133 MHz. The AMD-751 can queue 16 outstanding AGP transactions. See Chapter 5, “Functional Operation” starting on page 45 for more information. 10 ...
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... The AMD-751 system controller functions as a PCI target on the AGP bus. When the AGP bus functions in AGP mode, the graphics controller is the AGP initiator and the AMD-751, which contains the memory controller, functions as the AGP target. The AMD-751 implements a full-featured graphics-address remapping table (GART) ...
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... AMD-751™ System Controller Data Sheet 2.1.5 Block Diagram Figure 2 shows the full complement of features and functions built into the AMD-751 system controller system logic. SADDIN[14:2]# SADDINCLK# SADDOUT[14:2]# SADDOUTCLK# SDATA[63:0]# SDATAINCLK[3:0]# SDATAINVAL# SCHECK[7:0]# SDATAOUTCLK[3:0]# CLKFWDRST PROCRDY CONNECT Figure 2. AMD-751™ System Controller Block Diagram ...
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... SDRAM self-refresh and PCI master grant suspend. SDRAMs are put in a self-refresh mode by the deassertion of the MCKE[2:0] pins. The AMD-751 enters that mode in a Stop Grant state. Careful routing of this signal on the board is important to ensure that it stays clean when it is asserted or deasserted ...
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... Clocking The AMD-751 system controller receives a 100-MHz system clock and a 33-MHz PCI clock. The AMD-751 generates and drives the 100-MHz SDRAM clocks through a zero-delay buffer. The 66-MHz AGP clock is provided by the system clock generator as shown in Figure 3. It uses a non-JTAG, partial-scan scheme for silicon and motherboard testability (NAND tree) ...
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... AMD standard products are available in several packages and combination of the elements shown in Figure 4. Table 4 shows representative for detailed ordering information. AMD-751 Figure 4. Ordering Information Elements Table 4. OPN AMD-751AC 492-pin PBGA ATX Note: Chapter Case Temperature Package Type Family/Core Valid Combinations for Ordering Parts Package Type Operating Voltage 3.135 V– ...
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... AMD-751™ System Controller Data Sheet 16 Preliminary Information Ordering Information 21910E—March 2000 Chapter 3 ...
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... This signal is negated by RESET asserted off the rising edge of SYSCLK. 4.1.3 PROCRDY (Processor Ready) Input Summary PROCRDY is an input to the AMD-751 system controller and is used for power management and source-synchronous clock initialization at reset. Sampled This signal is sampled on the rising edge of SYSCLK. Chapter 4 AMD-751™ ...
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... SADDOUT[14:2]# (System Address Out) Input Summary The SADDOUT[14:2]# channel is the unidirectional system address interface from the processor to the AMD-751 system controller. The SADDOUT[14:2]# channel is used to transfer processor requests to the system. All commands on this channel are skew-aligned with the source-synchronous clock, SADDOUTCLK#. ...
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... Driven, Sampled, and ive s Floated SCHECK[7:0]# with valid data. As Inputs: During write cycles, the AMD-751 system controller samples SCHECK[7:0]#. SCHECK[7:0]# is floated out of RESET#. It remains floated except when driven with write data by the processor, by read data (writeback data) from the cache read data from the AMD-751 system controller ...
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... SDATAINCLK[3:0]# (System Data In Clock) Output Summary SDATAINCLK[3:0]# is the single-ended source-synchronous clock driven by the AMD-751 system controller to transfer data on SDATA[63:0]#. Each 16-bit data word is skew-aligned with this clock. Each edge is used to transfer data. Driven This signal is driven inactive (negated) when the CLKFWDRST signal is active (true) ...
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... SDATAINVAL# (System Data In Valid) Output Summary SDATAINVAL# is driven by the AMD-751 system controller and controls the flow of data into the processor. SDATAINVAL# can be used to introduce an arbitrary number of cycles between octawords (128 bits). Driven This signal is negated by RESET#. SDATAINVAL# is asserted off the rising edge of SADDINCLK ...
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... When the AMD-751 is the PCI target, these lines are inputs during the address and write data phases of a transaction, and outputs during the read data phases. ...
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... As Outputs: The AMD-751 system controller drives C/BE[3:0]# Floated with a valid command or byte enables off the rising edge of PCLK. As Inputs: When the AMD-751 system controller is a target, it samples C/BE[3:0]# on the rising edge of every PCLK. C/BE[3:0]# are qualified by FRAME# for commands and qualified by IRDY# and TRDY# for data. ...
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... Floated valid off the rising edge of PCLK. The duration of FRAME# varies with the length of the transfer Input: When the AMD-751 system controller is a target, it samples this signal on the rising edge of every PCLK. The assertion of FRAME# indicates the start of a cycle. FRAME# remains asserted during burst transfers ...
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... IRDY# and TRDY# are asserted together. Driven, Sampled, and As an Output: When the AMD-751 system controller is the PCI Floated initiator, it drives IRDY# asserted one PCLK after it asserts FRAME# and holds it asserted until one cycle before the end of all transactions ...
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... PCLK (PCI Clock) Input Summary PCLK is a 33-MHz clock provided by the system clock generator used by the AMD-751 logic in the PCI clock domain. PCLK to A_CLK (AGP clock) skew is +/– 500 ps maximum. 4.2.10 PGNT# (PCI Grant to Peripheral Bus Controller) Output ...
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... Asserting RESET# resets the AMD-751 system controller and sets all register bits to their default values. Bidirectional signals are three-stated and outputs are driven inactive. This signal is driven by the PCIRST# signal from the AMD-756 peripheral bus controller. Sampled This signal may be asynchronous to SYSCLK and PCLK synchronized internally, therefore it must be active for a minimum of four PCLK periods ...
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... As a PCI initiator, the AMD-751 system controller samples TRDY# to determine when the target agent is able to complete the data phase of a transaction PCI target, the AMD-751 asserts TRDY# to indicate that it has latched the data on AD[31:0] during a write phase or driven the data on AD[31:0] during a read phase. ...
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... The AMD-756 peripheral bus controller requests that the AMD-751 system controller issue a Fence command to its buffers by placing a single PCLK pulse on WSC#. The AMD-751 then marks the data currently in its buffers and waits for this data to reach processor-accessible (coherent) space. When this ...
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... AMD-751™ System Controller Data Sheet 4.3 DRAM Interface Signals 4.3.1 CS[5:0]# (Chip Selects) Output Summary CS[5:0]# function as chip select signals for SDRAMs. Driven These signals are negated by RESET#. The memory controller asserts or negates these signals off the rising edge of SYSCLK at the appropriate time in the memory access sequence. See Chapter 5, “ ...
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... MDAT[63:0] (Memory Data) Bidirectional Summary MDAT[63:0] connect to the DRAM data I/O. They are driven by the DRAM during reads and are driven by the AMD-751 system controller during writes. Driven, Sampled, and As Outputs: These signals are driven with the data to be written Floated on the rising edge of SDRAM_CLKOUT ...
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... MECCD[7:0] (Memory ECC) Bidirectional Summary MECCD[7:0] carry error correction codes for the eight bytes of data on MDAT[63:0]. These signals are inputs to the AMD-751 system controller during DRAM read cycles and outputs during DRAM write cycles. Driven, Sampled, and As Outputs: These signals are driven with the parity or ECC Floated data on the rising edge of SYSCLK ...
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... SDRAM Clk_Out is a clock signal for the synchronous DRAM. Driven This signal is a free-running clock generated by the internal PLL in the AMD-751 system controller. This signal is used to clock a zero delay buffer (ZDB) external to the AMD-751. The ZDB, in turn, generates the clock for the SDRAMs. The advantage of the ZDB is that the timing of the clocks to the SDRAM DIMMs can be adjusted ...
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... Floated controller drives A_AD[31:0] with ADSTB[1:0] during data transfers to the graphics controller from the system controller. In multiplexed mode, the AMD-751 drives A_AD[31:0] with a valid address or data off the rising edge of SYSCLK during the return of read requests. In addition, A_AD[31:0] are driven during processor writes to the graphics controller. ...
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... SYSCLK when A_FRAME# or PIPE# is asserted. The AMD-751 drives A_C/BE[3:0]# with valid byte enables off the rising edge of SYSCLK when A_FRAME# or PIPE# is negated. As Inputs: When the AMD-751 system controller is a target, it samples A_C/BE[3:0]# on the rising edge of SYSCLK. A_C/BE[3:0]# are floated during reset and when the bus is idle. ...
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... A_GNT# (AGP Bus Grant) Output Summary As the AGP bus arbiter, the AMD-751 system controller asserts A_GNT# in response to A_REQ# from the initiator (graphics controller) to indicate to the initiator that it has been granted control of the bus. At the same time, the system controller provides status information on status signals ST[2:0] to indicate to the initiator whether supply data or receive data in response to a previously queued request ...
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... SYSCLK. For AGP transfers, A_IRDY# is asserted for one clock. For PCI transfers driven during the entire transaction Input: When the AMD-751 system controller is a target, it samples A_IRDY# on the rising edge of SYSCLK. For AGP transfers, A_IRDY# is sampled only at the beginning of a cycle. ...
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... If a transfer is larger than one block, A_TRDY# must be reasserted for each block. Asserting A_TRDY# every four clock cycles completes the transfer without wait states AGP initiator, the AMD-751 samples A_TRDY# to determine if data is ready to be transferred. 38 Preliminary Information Signal Descriptions 21910E— ...
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... In AGP-multiplexed mode, data remains on the bus until A_TRDY# is asserted. In AGP-demultiplexed mode, A_TRDY# is asserted for one clock for each block transferred Input: When the AMD-751 system controller is an initiator, it samples A_TRDY# on the rising edge of SYSCLK. For AGP transfers, A_TRDY# is sampled only at block boundaries ...
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... SYSCLK. When the AMD-751 system controller is an initiator, it uses the rising and falling edges of ADSTB0 to clock data into the target Input: When the AMD-751 system controller is a target, it uses the rising and falling edges of ADSTB[1:0] to clock data into its internal registers. ...
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... RBF# (Read Buffer Full) Input Summary An AGP initiator asserts RBF# to indicate that its buffers are full AGP target, the AMD-751 system controller cannot commence a low priority data read to the initiator until it samples RBF# negated. RBF# does not apply to high-priority read data. ...
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... SBSTB (Sideband Strobe) Input Summary Sideband strobe is a synchronization clock generated by the AGP initiator for SBA[7: mode. The AMD-751 system controller uses SBSTB to strobe in commands on the SBA bus to its request queue. SBSTB is driven continuously by the graphics device—NOPs are strobed when no command is present ...
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... Bidirectional Summary ROM_SCK drives the CLK pin of the debug SROM. If this signal is pulled High during RESET#, the SROM supplies the SIP packet. If this signal is pulled Low, the SIP packet is generated internal to the AMD-751 system controller. 4.6.2 ROM_SDA (SROM Data) Bidirectional Summary ROM_SDA connects to the data pin of the debug SROM ...
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... AMD-751™ System Controller Data Sheet 44 Preliminary Information Signal Descriptions 21910E—March 2000 Chapter 4 ...
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... Functional Operation This section details the operation of the AMD-751 system controller. 5.1 System Addressing Overview The AMD-751 system controller supports the AMD Athlon system bus specification. The AMD Athlon processor contains mapping logic for all legacy x86 addresses through an address map (see Table 5 on page 46) ...
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... This address space can be used by the AMD-751 for (Blocks) undefined purposes. DRAM, accessed with read and write block commands. Normal Memory Note: The AMD-751 only uses 32 address bits internally and (Blocks) the address space wraps. Address 1 0000 0000 is treated the same as 0 0000 0000. Functional Operation 21910E— ...
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... Figure 6 shows the x86 view of memory from the perspective of the AMD Athlon processor, and mapping to the AMD Athlon system bus memory map. I/O Space 0CF8h, 0CFCh x86 In and Out Address Space APIC Registers PCI Memory Reserved AGP Virtual ...
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... AMD-751™ System Controller Data Sheet Special Cycles There are seven special cycles generated by the AMD Athlon processor that are passed onto the PCI bus with specific values in the address and data fields of the PCI special cycle command. Table 6 defines these values (same value for address and data) ...
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... The AMD-751 optionally (through device 0, offset 60, bit 17) initiates an AMD Athlon system bus disconnect to the processor. The AMD-751 forwards onto the PCI bus (after the optional AMD Athlon system bus disconnect) a PCI special cycle command—AD[31:0] = 0012 0002 (address and data). ...
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... RdBytes/Rd/LWs and WrBytes/WrLWs AMD Athlon system bus commands. Command Address Decoding logic in the AMD-751 processor and PCI interfaces Decoding provides a consistent view of memory and PCI devices. The AMD-751 considers the processor’s request and Physical Address (PA) fields when decoding a command. This command ...
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... Chapter 5 AMD-751™ System Controller Data Sheet Using device 0, offset 14h, BAR1, the access is directed to AMD-751 memory mapped GART control registers (see Chapter 7, “Configuration Registers” on page 123). Using device 1, offset 20h and device 1, offset 22h, memory base and limit registers, the access is directed to either PCI or AGP/PCI using address bits 31– ...
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... Register Access PCI configuration registers. Configuration accesses in the AMD-751 conform to the following rules: n The AMD-751 is defined to be device 0 and device 1. All external PCI devices must be wired to one of the AD[31:13] wires. Logically, AD[12:11] are assigned to devices 0 and 1 in the AMD-751 system controller. ...
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... Processor Interface This section describes the interface logic between the AMD Athlon processor and the AMD-751 system controller. 5.2.1 Bus Interface Unit (BIU) The bus interface unit (BIU) is the interface between the processor and the rest of the system. The BIU receives commands and probe responses from the processor and issues probes to the processor ...
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... The AMD Athlon system bus is a unique, source-synchronous, channel that uses protocol and fixed delivery windows to provide maximum performance. An AMD Athlon system bus is synchronous. However, the use of multiple PLLs in the system and the use of source-synchronous clocking create different clock domains from the processor to the system logic and from the processor to a backside L2 cache ...
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... As part of the reset sequencing, the processor and system logic use a set of shared interface pins (CONNECT, CLKFWDRST, and PROCRDY) to serially transfer a serial initialization packet (SIP) from a ROM table in the AMD-751 to the processor. Resister strapping options on the AMD Athlon system bus card-edge connector select the entry in this ROM table. The strapping tells the AMD-751 what speed and what processor type is in the processor module ...
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... Note: The system must be out of reset before the processor deasserts PROCRDY. One or more SYSCLK periods after the deassertion of PROCRDY, the system deasserts CLKFWDRST. (States 3 and 3 4 are performed for AMD Athlon system bus legacy reasons.) 4 One or more SYSCLK periods after the deassertion of CLKFWDRST, the system again asserts CLKFWDRST. ...
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... SIP protocol. The AMD-751 implements two modes — production and debug. During reset, if ROM_SCK is pulled High (debug mode), the SROM supplies the SIP packet to the AMD-751. If ROM_SCK is pulled Low (production mode), the SIP packet is generated internally. 5.2.3 Processor Write Posting The AMD-751 system controller contains two write buffers to enhance write performance ...
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... Write buffers continue to accept data until either the buffers are full or all data from the processor is received. At that point, the AMD-751 begins writing data to the DRAM. As each pending write to main memory is performed, freeing the corresponding buffer, the memory controller sends a command to the processor ...
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... Memory Interface The AMD-751 system controller memory interface contains two functional blocks — the memory request organizer (MRO), which serves as a data crossbar and kernel for the AMD-751, and the memory controller (MCT), which is designed to operate up to three PC-100 SDRAM DIMMs. ...
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... AMD-751™ System Controller Data Sheet From BIU From AGP AGP Address Translator (AAT) MRQ3 MRQ2 Figure 10. Memory Request Organizer (MRO) Block Diagram Memory Queue The memory queue arbiter (MQA) is responsible for choosing Arbiter (MQA) between read and write requests from all sources (BIU, PCI, and A-PCI round-robin (RBN) manner ...
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... The RBN schedules the read request to the MCT in a round-robin manner. Chapter 5 AMD-751™ System Controller Data Sheet Force Priority Request Two-Input Round-Robin Arbiter ...
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... AMD-751™ System Controller Data Sheet When the entry is put into the MRQ, the address of the read request is passed through the memory write queue (MWQ) and compared with all valid MWQ entries. If one or more write requests in the MWQ are pending to the same cache line ...
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... Next Request Accept Request SDRAM Interface Note: * BIU data bypasses ECC generation and passes the system bus ECC directly to memory. Figure 12. Memory Controller (MCT) Block Diagram Chapter 5 AMD-751™ System Controller Data Sheet Data Request Accept Request Data Acknowledge GART ...
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... Support for up to four open pages within one CS (the device selected by chip select) for one-quadword AGP requests. n Support for ECC with no scrubbing or correction of memory. ECC from the AMD Athlon system bus is passed directly into memory without checking and regeneration. No support for parity generation and checking is provided. ...
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... SDRAM organization. The memory organizations listed in Table 8 on page 66 for 16-Mbit and 64-Mbit SDRAM are from current SDRAM specs and from the JEDEC standard. Chapter 5 AMD-751™ System Controller Data Sheet Functional Operation 65 ...
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... AMD-751™ System Controller Data Sheet . Table 8. SDRAM Memory Organizations Number of SDRAMs SDRAM Organization Needed for 64-Bit Bus 4-Bit Wide Device 16 Two Banks x 2 Mbytes 8-Bit Wide Device Two Banks x 1 Mbyte 16-Bit Wide Device Two Banks x 512 Kbytes 32-Bit Wide Device Two Banks x 256 Kbytes — ...
Page 81
... BIOS can use the serial presence detect (SPD) feature found in PC-100 DIMMs (using the AMD-756 peripheral bus controller to read DRAM information AMD Athlon™ BIOS Developers Guide, order# 21656 for more information. Error Correcting The AMD-751 system controller supports error correcting code ...
Page 82
... ECC that is stored in the DRAM parity bits. If this procedure is not performed, errors occur when writing data smaller than a 64-bit quadword. Data from the AMD Athlon processor includes ECC, which is passed directly into memory— providing protection along the whole data path. ...
Page 83
... SMCBusyCS[7:0] Refresh State Machine CS3 CS4 CS5 Refresh Refresh Refresh Counter Counter Counter Pick 1 CS Functional Operation AMD-751™ System Controller Data Sheet · Clock Period -9 (1536 cycles) ( sec) RefAccept RefCS, Addr, CMD, V RefCS Busy To Memory Request Arbiter (MRA) 69 ...
Page 84
... AMD-751™ System Controller Data Sheet SDRAM Initialization This section contains basic information about SDRAM initialization. For more details, see the AMD-751™ System Controller Memory Settings Application Note, order# 22835. Initialization can be broken down into two parts. The first is the SDRAM initialization and the second is the BIOS initialization to configure the MCT for correct and optimal operation ...
Page 85
... RAM and making that area read-only. The portion of RAM containing the BIOS copy is referred to as shadow RAM. The AMD-751 system controller does not contain any hardware to support the shadowing of system, video, and other BIOS functions to accelerate access. This capability is supported with the AMD Athlon processor memory type and range registers (MTRR) ...
Page 86
... AMD-751™ System Controller Data Sheet 5.3.6 Synchronous DRAM (SDRAM) The AMD-751 system controller only supports synchronous DRAM (SDRAM), which is a cost-effective, mainstream type of system memory. SDRAMs use a clock to synchronize address and data rather than row and column strobes. The net effect is burst performance that approaches SRAM ...
Page 87
... Multiple Pages Open Using SDRAM, the AMD-751 system controller allows multiple pages in a DIMM module to be open at the same time, which increases the effective memory bandwidth by eliminating some RAS cycles. SDRAM at 100 MHz When using SDRAM on a 100-MHz memory bus, some special considerations and analysis are required ...
Page 88
... AMD-751™ System Controller Data Sheet Table 10 gives a more detailed SDRAM DIMM loading analysis. Table 10. SDRAM DIMM Loading Analysis DIMM DIMM SDRAM Size Organization Technology 8 Mbytes 1 Mbyte Mbit x16/16 Mbit 8 Mbytes 1 Mbyte Mbit x16/16 Mbit 16 Mbytes 2 Mbytes Mbit x16/16 Mbit 16 Mbytes 2 Mbytes Mbit x16/16 Mbit ...
Page 89
... The SDRAM 100-MHz To achieve the 100-MHz timing, a careful system timing analysis Scheme is required. Figure 16 shows the AMD-751 system controller clocking scheme. System Clock Generator SysCLK (100 MHz) AMD-751™ System Controller SDRAM CLK_Out SDRAM CLK_In Figure 16. AMD-751™ System Controller Clocking Scheme ...
Page 90
... AMD-751™ System Controller Data Sheet 0ns clock early clock late clock MA MA (delay) SRAS#,SCAS#,WE# ctrl (delay) MD (write) MD (write delay) MD (read) MD (read delay) Figure 17. 100-MHz SDRAM Detailed Timing 76 Preliminary Information 50ns tsu th tSU tsu tVD tVD tprop tVD tVD tprop ...
Page 91
... Tdimm 1 1 Trrd 2 2 Signal Timing Analysis. The following equation calculates how early the AMD-751 system controller needs to send out SDRAM address and control signals. The calculation is as follows, with the reference as the external system clock: t prop Where between the AMD-751 and SDRAM = 0.325 ns ...
Page 92
... This module contains write buffers (PCI-to-memory and PCI-to-PCI), read buffers from memory, and a target sequencer that keeps track of the bus while the AMD-751 is a PCI target. Memory requests from both the PCI interfaces are sent through the MRO. See “AGP System DRAM Interface (SDI)” on page 90 for more information ...
Page 93
... PCI bus among itself, the AMD-756 peripheral bus controller, and five other PCI initiators. When there are no requests for the bus, ownership defaults to the processor through the AMD-751. Parking the bus in this ma nner is s ome tim rred to as processo r-ce nt ric rog memory-centric, which parks the bus on the PCI master ...
Page 94
... On the PCI Bus The AMD-751 does not check parity on the PCI bus. The status bit (device 0, offset 07h–06h, bit 8) is always zero. 5.4.6 PCI-to-Memory/PCI-from-Memory and Other PCI Targets The PCI target memory write FIFO is used to gather PCI writes-to-memory into cache lines ...
Page 95
... PCI bus. 5.4.8 Processor-to-PCI Bus Write Transactions The AMD -7 51 syst roller converts a f ull 64 -bit (quadword) processor-to-PCI write into two consecutive 32-bit (doubleword) PCI write cycles. This feature reduces the bus bandwidth required to complete PCI writes. ...
Page 96
... A PCI initiator begins a memory read or write cycle by asserting FRAME# and placing the memory address on AD[31:0]. The AMD-751 system controller decodes the address. If the address is within the domain of the processor or memory, the AMD-751 accepts the cycle and responds as a PCI target by asserting DEVSEL#. If the address is not within the AMD-751 or processor domain, the AMD-751 ignores the cycle and allows it to complete on the PCI ...
Page 97
... Write Data and Byte The PCI data bus is 32 bits wide while main memory and Enables internal data buses within the AMD-751 are 64 bits wide. When a PCI write occurs to memory (and the other PCI interface), two consecutive doublewords are accumulated into a quadword of data ...
Page 98
... MHz). n Freedom from the coherency requirements of PCI, which eliminates the latency resulting from cache snooping. n Full PCI 2.2 capability, which enables the AMD-751 to pass programming information from the processor to the graphics adapter deep request queue. ...
Page 99
... If the corresponding GART entry is not present, a request is sent to the ATE, a GART table walk is performed, and the entry is fetched from the memory. Chapter 5 AMD-751™ System Controller Data Sheet TLB Miss AGP Write Data WRQ GART ...
Page 100
... Because the output of these two request queues goes to different blocks, they can both send out requests at the same time. The AMD-751 queues and data buffers streamline AGP read and write requests and data transfers. These queues and buffers are shown in Figure 19 on page 87. ...
Page 101
... The read request queue (RDQ) interfaces to the SDI and the read acknowledge queue (RXA). n Requests can be issued from both the write queue and read queue in the same clock. Chapter 5 AMD-751™ System Controller Data Sheet DRAM Controller and GART Table Walk AGP Interface Transaction ...
Page 102
... AMD-751™ System Controller Data Sheet Structure of the AGP The AGP request queue is split up into two queues — one for Request Queue read requests and one for write requests. Because there is a reordering FIFO in the address module, the request queues do not have to be large. The read queue is big enough to hold all outstanding read requests, which avoids stalling writes that run on the bus while the reads are being done on memory ...
Page 103
... A single quadword of random data is returned when the last write is completed. This process forces all data residing in the AMD-751 system controller buffers to be visible to the rest of the system, ensuring that a subsequent memory access returns the correct AGP data. ...
Page 104
... The SDI sub-block checks that the address is cache-line (or four quadword) aligned not aligned, the AMD-751 system controller requests single quadwords. Otherwise, the AMD-751 requests an entire block (eight quadwords). In addition, in the case of writes, if all the bytes in the transaction are not enabled and if ECC is enabled, the transaction is broken down into single quadword transfers ...
Page 105
... AGP bus. In addition, the AGP arbiter can generate pipelined data grants to get the maximum bandwidth. There are three different arbiters in the AMD-751 system controller—the PCI arbiter, the memory arbiter, and the AGP arbiter. The relationship between these three arbiters and their various inputs is shown in Figure 20 ...
Page 106
... AMD-751™ System Controller Data Sheet PCI Arbiter The PCI arbiter receives requests from the processor, the AMD-756 peripheral bus controller, and other PCI agents, and determines which request is serviced on the PCI bus. Memory Arbiter The memory arbiter receives requests from the processor, the PCI arbiter, and the AGP request queue ...
Page 107
... However, data coherency is lost. Data transfers requiring coherency should be transferred with PCI cycles. To service an AGP read request, the AMD-751 system controller reads the requested data from memory, stores it in its 64-quadword read data FIFO, and sends it to the adapter during AGP data phases ...
Page 108
... A graphics adapter requires a contiguous view of memory, but most systems allocate memory in non-contiguous blocks. To accommodate this disparity, the AMD-751 system controller implements a graphics adapter remapping table (GART) described in the AGP Interface Specification, Revision 2.0. The ...
Page 109
... AGP specification. Each entry in the table(s) correlates a virtual address with a physical address. Configuration registers in the AMD-751 system controller determine the location of the table(s) in memory, and the location and size of the AGP memory block to which the GART translates its addresses. ...
Page 110
... AMD-751™ System Controller Data Sheet Figure 22 and Figure 23 show the GDC and GTC hierarchy. See “GART Cache Operation” on page 98 for more information. Figure 22. Cache Hierarchy (Conventional Two-Level Scheme) Virtual Address A[31:22] Physical Address of GART table Master A[31:12] Table Cached in GDC Figure 23. Conventional GART Scheme— ...
Page 111
... Base Addresses Note: Page Table Entries (PTE) contain the page base addresses or the page frame address Figure 24. Page Translation Structures Chapter 5 AMD-751™ System Controller Data Sheet 12 4 Kbytes 4 Kbytes Page Table Page Table Entries Cached in GTC Functional Operation Physical Memory ...
Page 112
... GART Front End Page Tables Entry GART Table Cache The AMD-751 system controller contains three GART table caches (GTCs) and an 8-entry GDC. In the two-level scheme, a virtual address that hits the GTC cache can be translated to its physical address without any memory accesses. Missing the GTC, but hitting the GDC cache requires only one memory access ...
Page 113
... GART by the miniport driver when 4-Kbyte pages are reserved by the graphics application. For texture data, the page is usually uncacheable. For geometry data advantageous for the page to be cacheable. Chapter 1=Present and Valid 0=Not Present/Page Not Valid Number Pages Functional Operation AMD-751™ System Controller Data Sheet ...
Page 114
... AMD-751™ System Controller Data Sheet Distributed GART— The GART directory cache (GDC) contains three GART table GDC Features caches (GTC)—one each for the processor, AGP, and PCI/A-PCI. These GTCs have the following features: n The AGP GTC is a 16-entry, fully associative cache. ...
Page 115
... Table #1 Memory Access Table #2 Memory Access Physical Page Address A31–A12 Figure 26. Address Translation Flow Chart Chapter GART range? Yes Miss Request to GTW GTW Yes Hit Miss Functional Operation AMD-751™ System Controller Data Sheet Bypass (No Translation) Physical Address = Virtual Address 101 ...
Page 116
... AMD-751™ System Controller Data Sheet Page Directory Entry Each PDE is 32-bits wide. Bits 31–12 form bits PA[31:12] of the (PDE) physical address (PA) used to fetch the PDE. Bits 11–2 are formed by bits 31–22 of the linear address provided by the graphics master. Bits 11–8 of the PDE are reserved for future use, bits 7– ...
Page 117
... Fetch Operand from Memory Figure 27. Two-Level GART Translation Scheme Chapter Page Table Offset Page Offset 12 11 Page Directory Offset (from linear address Page Table Offset (from linear address Page Offset (from linear address) Functional Operation AMD-751™ System Controller Data Sheet 103 ...
Page 118
... AMD-751™ System Controller Data Sheet 1-Kbyte Table Entries GART Table 1-Kbyte Table Entries GART Directory Directory Entry 2 (up to 1-Kbyte Directory Entry 1 entries) Figure 28. Another View Of the Two-Level Indexing Scheme GTC Data The GTC supports the referencing of a variable number of pages by one GTC entry. The GTC allows for some virtual ...
Page 119
... VPA, and a 20-bit PPA. When a new VPA is available compared with all 16 tag entries in parallel. If one of the 16 parallel address comparators corresponding Hit[15:0] signal selects the correct PPA through the output multiplexer. Chapter 5 AMD-751™ System Controller Data Sheet Functional Operation 105 ...
Page 120
... System Bus AMD Athlon™ Processor Figure 29. Power Management Signal Connections As shown in Figure 29, the processor and the AMD-751 system controller communicate power state transitions through the AMD Athlon system bus connect/disconnect protocol and special cycles (masked writes to a defined AMD Athlon system ...
Page 121
... The AMD-751 system controller disables PCI/AGP 2. The AMD-751 completes the AMD Athlon system bus 3. The AMD-751 sends a Stop Grant special cycle on the 4. The AMD-756 peripheral bus controller receives and Halt special cycles are generally considered part of an ACPI state definition (C1) ...
Page 122
... AMD-751 power management state machine (PMSM). The two basic power states are described in this section. Full-On (C0). In this state the AMD-751 system controller is fully operational, all clock trees are running, and the AMD-751 provides refresh to the SDRAMs. ...
Page 123
... Request from PCI/AGP Wait for Self-Refresh Self-Refresh Exit Self-Refresh Exited Connect Done C2 Disconnect Pending Running Disconnect Abort Functional Operation AMD-751™ System Controller Data Sheet C0 Wait For Idle Flush Wait for Self-Refresh Entered Wait for Exit Self-Refresh Exit Self-Refresh Exited Wait ...
Page 124
... PLL Clock Outputs The PLL has two output clocks that are distributed throughout the AMD-751. The peripheral clock, which runs at 66 MHz, is used by all the sequencers and logic controlling the peripheral buses (PCI and AGP). The standard PCI logic runs internally at 66 MHz ...
Page 125
... Typical Settings Table 14 lists typical MSR settings for the AMD-751 system controller. Table 14. AMD-751™ System Controller MSR Settings Register Bit Description Func:Reg 0:0x10 31:25 AGP base address high Base low, prefetchable, type, 24:0 memory GART memory mapped register ...
Page 126
... AMD-751™ System Controller Data Sheet Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg 6:1 Bank address mask [28:23] 0 Bank enable 0:0x50, 0:0x51, 7 Reserved 0:0x52 6 Bank(x+1) address mode Number of banks in bank(x+1) 5 (internal DRAM banks on a DIMM) 4:3 ...
Page 127
... Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg 21:20 SDRAM AddrA Drv SDRAM CAS[2:0], RAS[2:0], 19:18 WE[2:0], CKE[2:0], CS[5:0] drive 17:16 SDRAM DQM drive Page Hit request before a 15:14 non-Page Hit Idle cycle to wait before ...
Page 128
... AMD-751™ System Controller Data Sheet Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg 1:0 Trcd (RAS to CAS latency) 0:0x58 31:26 Reserved 25 SDRAM init SDRAM type (reserved for future use – SDRAM, 1 – ESDRAM Mode register status (read/write ...
Page 129
... Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg One hot encoded chipselect of 5:0 request that generate the single or multi-bit error Probe enable for CPU0 0:0x60 31 (0 – disable, 1 – enable) 30 Lck Half C2M 29 Lck Half M2C ...
Page 130
... AMD-751™ System Controller Data Sheet Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg Ack limit 0000 – 1 un0acked command 13:10 0001 – 2 …. 1111 –- 16 Bypass Enable 1 – System controller bypasses 9 certain memory to processor pipe stages for optimal ...
Page 131
... Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg PCI pipe enable 0 – MRO checks outstanding read probe before PCI 10 transactions 1 – MRO pipelines PCI transactions PCI Block Write Enable 0 – BIU performs RID/INV probes, forcing MRO MWQ ...
Page 132
... AMD-751™ System Controller Data Sheet Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg AGP VGA BIOS address decode Bit31: 0D_C000 – 0D_FFFF 0:0x84 31:24 Bit30: 0D_8000 – 0D_BFFF … Bit24: 0C_0000 – 0C_3FFF 23:18 Reserved Enable APC chaining 17 1 – ...
Page 133
... Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg Dis APC Early Probe 1 – disable early snoop from 11 AGP master running a PCI cycle to memory Dis PCI Early Probe 1 – disable early probe request 10 for write cycles from an ...
Page 134
... AMD-751™ System Controller Data Sheet Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg Target latency timer disable 1 – disable AMD-751 system 3 controller target latency timer on both PCI and AGP’s PCI interfaces ApcPreEn 1 – enables AMD-751 to ...
Page 135
... Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg 7:6 Reserved Greater than 4G address support 5 0 – disable 4:2 Reserved AGP data transfer mode 1:0 01b – 1x 0:0xAC 31:17 Reserved VGA ISA address decoding 0 – no ISA aliasing on address ...
Page 136
... AMD-751™ System Controller Data Sheet Table 14. AMD-751™ System Controller MSR Settings (Continued) Register Bit Description Func:Reg Non-GART Snoop 0 – AGP address falling outside 19 GART do not cause probes 1 – enable probes Post GART queue size 18 0 – 8 entries entries GART page directory cache ...
Page 137
... Configuration accesses in the AMD-751 system controller conform to the following rules: The AMD-751 is defined to be device 0. The IDSEL pin on every external PCI device must be wired to one of the AD[31:12] lines, because logically AD[11] is assigned to device 0. Device 0 accesses correspond to the Processor-to-PCI bridge registers listed in Table 16 on page 126 and defined starting on page 130 ...
Page 138
... AMD-751 passes this field through to the AD bus undecoded to select the defined device. Devices are assigned a number by tying the device IDSEL# pin to a PCI AD line. The AMD-751 system controller uses device 0 and device 1, which correspond to AD11 and AD12, respectively. Device 0 (00000b) is the standard Processor-to-PCI bridge registers ...
Page 139
... Configuration data is a read-write port that responds only to doubleword accesses. Byte or word accesses are passed on unchanged. Note: In the AMD-751 system controller, IDSEL is internally connected to AD11. Other PCI devices in a system must connect their IDSEL lines to a unique line in AD[31:12] and cannot use AD11. ...
Page 140
... AMD-751™ System Controller Data Sheet 7.2 Register Overview Table 16 through Table 18 summarize the AMD-751 system controller configuration register offsets, devices, default values after reset, and access types. Access types are indicated as follows: RW Read/Write RO Read Only RWC Read and/or write 1’s to clear individual bits ...
Page 141
... B0h AGP Mode Control Register #1 B2h AGP Mode Control Register #2 Note changes for each device revision. For more information, see 7.2.1 “Revision ID Nomenclature” on page 129. Chapter 7 AMD-751™ System Controller Data Sheet Cache Control Reset 0000h 0000h 00h 00h 00h ...
Page 142
... AMD-751™ System Controller Data Sheet Table 17. Function 0, Device 1 Configuration Registers Offset 01h–00h Vendor ID 03h–02h Device ID 05h–04h AGP/PCI Command 07h–06h Status 08h AGP Revision ID 09h Programming Interface 0Ah Subclass Code 0Bh Base Class Code 0Ch Reserved 0Dh ...
Page 143
... Power Management Configuration Registers (BAR2 + n) Offset 01h–00h PM2 (Power Management) 7.2.1 Revision ID Nomenclature Table 20 shows possible revision and stepping enumeration for the AMD-751 system controller. For more information, see “Revision ID Device 0 Offset 08h” on page 133. Table 20. Revision ID Enumeration Revision (Bits 6:4) Hex Pattern 0h ...
Page 144
... This read-only value is defined as 1022h. Device ID Bit Reset This read-only value of 7006h represents the AMD-751 system controller single processor device. Command Bits 15–10 Reserved Reset Bits 15–10 Reserved (always reads 0) Bit 9 Fast Back-to-Back Cycle Enable (always reads 0)—Fast back-to-back cycles are not supported ...
Page 145
... Initiator Enable (always reads AMD-751 system controller can behave as bus initiator Bit 1 Memory Space (RW Disable PCI memory space (default Responds to PCI memory space accesses Bit 0 I/O Space (always reads 0)—The AMD-751 does not act as an I/O target. Status Bit DPE SERR# ...
Page 146
... Received Initiator Abort (RWC)—This bit is set by a PCI initiator when its transaction is terminated with initiator abort PCI transactions proceeding normally 1 = The AMD-751 system controller has detected that a transaction was terminated before completion Bit 12 Received Target Abort (RWC)—The target issues a target abort when it detects a fatal error or cannot complete a transaction ...
Page 147
... Base Class Code (always reads 06h)—The PCI-defined base class code for a bridge device is 06h. Reserved Bit 7 6 Reset 0 0 Bits 7–0 Reserved (always reads 00h) Chapter AMD-751 System Controller Chip Revision and Stepping Code — — — Programming Interface Subclass Code ...
Page 148
... PCI clocks 00000001–11111111 = (8-bit binary value) x PCI clocks Header Type Bit 7 6 Reset 1 0 Bits 7–0 PCI Header Type (RO)—The AMD-751 system controller PCI header type is 80h, indicating a multifunction device. Reserved Bit 7 6 Reset 0 0 Bits 7–0 Reserved (always reads 00h) ...
Page 149
... Bit 29 Bit 28 Bit 27 Bit Configuration Registers AMD-751™ System Controller Data Sheet Device 0 Offset 13h–10h Bit 3 Bits 2–1 Pre Type Memory Bit 25 Allocated 1 32 Mbytes 0 64 Mbytes 0 128 Mbytes 0 256 Mbytes 0 512 Mbytes 0 1 Gbytes 0 2 Gbytes Bit 0 Mem 0 135 ...
Page 150
... AMD-751™ System Controller Data Sheet Base Address Register 1 (BAR1) Bits 31–12 Base Address High Reset This register is used by the AGP driver software to set the memory location of the AGP memory-mapped control registers. Bits 31–12 Base Address High (RW) (default = 000000h)—This field is loaded by BIOS firmware to determine the base address A[30:11] of the memory-mapped AGP registers (BAR1) ...
Page 151
... Reserved (always reads 0) Bits 7–0 CAP_PTR (always reads A0h)—This field contains the PCI device 1 offset of the configuration register group in the AMD-751 system controller specifically reserved for AGP functions. This register group is the first item in the New Capabilities mechanism described in an amendment to the PCI Local Bus Specification, Revision 2 ...
Page 152
... AMD-751™ System Controller Data Sheet Base Address Chip Select Register 1 Bits 15–7 Bank 1 Base Address A[31:23] Reset Bits 15–7 Bank 1 Base Address A[31:23] (RW)—See Base Address Chip Select Register 0 on page 137. Bits 6–1 Bank 1 Address Mask A[28:23] (RW)—See Base Address Chip Select Register 0. ...
Page 153
... Bank 5 Address Mask A[28:23] (RW)—See Base Address Chip Select Register 0. Bit 0 Bank 5 Enable (RW Memory bank is disabled (default Memory bank enabled Chapter Configuration Registers AMD-751™ System Controller Data Sheet Device 0 Offset 49h–48h Bits 6–1 Bank 4 Address Mask A[28:23 Device 0 Offset 4Bh–4Ah Bits 6–1 Bank 5 Address Mask A[28:23 ...
Page 154
... AMD-751™ System Controller Data Sheet SDRAM Address Mapping Control Register 1/0 Bit 7 6 Reserved Address Mode 1 Reset 0 0 Bit 7 Reserved (always reads 0) Bits 6 CS1 Address Mode (RW)—This bit specifies the row and column addressing as shown in Table 22 on page 142. Bit 5 Number of Banks in CS1 (RW)— ...
Page 155
... CS4 Address Mode (RW)—This bit specifies the row and column addressing as shown in Table 22 on page 142. Bit 1 Number of Banks in CS4 (RW)—This bit specifies the number of internal DRAM banks in this chip select Two banks (default Four banks Bit 0 Reserved (always reads 0) Chapter 7 AMD-751™ System Controller Data Sheet #Banks 5 Reserved Configuration Registers ...
Page 156
Table 22. Mapping Processor Address Lines to Memory Address Lines Reg 50h MA14 MA13 MA12 MA11 MA10 MA9 Addr Mode 0 Row 11 16 Mbit Column 11 1 Row Mbit Column 128 ...
Page 157
... TRP SRAS Precharge (RW)—These bits specify the delay from precharge command to activate command cycle (default) (recommended safe configuration cycles cycles Chapter TRC TRP Configuration Registers AMD-751™ System Controller Data Sheet Device 0 Offset 55h–54h TRAS TCL TRCD Bit 0 0 143 ...
Page 158
... AMD-751™ System Controller Data Sheet Bits 6–4 TRAS Value (RW)—These bits specify the minimum bank (SRAS[2:0]#) active time. 000 = 2 cycles (default) 001 = 3 cycles 010 = 4 cycles 011 = 5 cycles 100 = 6 cycles 101 = 7 cycles (recommended safe configuration) 110 = Reserved 111 = Reserved Bits 3–2 TCL SDRAM SCAS Latency Value (RW)— ...
Page 159
... ECC CS Status (RO)—This field indicates the chip select where the ECC error occured. Bit 0 indicates CS0, bit 1 indicates CS1, etc. Chapter ECC Status Reserved Configuration Registers AMD-751™ System Controller Data Sheet Device 0 Offset 59h–58h Failing ECC Chip Select Bit 0 0 145 ...
Page 160
... SDRAM Type (RW0 SDRAM (default ESDRAM (not supported by the AMD-751 system controller) Bit 7 Mode Write Enable (RW)—This bit is used by the BIOS to set the DRAM mode register. TCL and Large Burst Enable must be set before this bit is asserted (see page 144). The MCT clears this bit when the mode register write is complete ...
Page 161
... AMD Athlon system bus grants for Write transfers allowed before the AMD-751 forces another type of transfer to gain access to the AMD Athlon system bus. The count limit prevents one type of transfer from dominating the AMD Athlon system bus. The recommended value is 100b ...
Page 162
... PCI or APCI operations are pending. This mode is valid for use in AMD Athlon processor systems only. Note: Bypass mode is available in Revision C and later of the AMD-751 system controller. In previous revisions, this bit was used as the RIH enable control. RIH probes are always disabled. ...
Page 163
... Bit 31 Clock Forward Offset (RW)—This affects the clock forwarded data bus timing AMD-751 system controller delays the assertion of SDATA [31:16] and [63:48] bits and appropriate clocks by approximately 1000ps All data groups are forwarded at the same time (nominally aligned with a system clock edge) Bits 30– ...
Page 164
... PCI Block Write Fast Enable (RW)—This bit should be set to 1 for optimal operation. When set, the AMD-751 system controller sends an NOP invalidate probe to the AMD Athlon processor for PCI block writes and allows the PCI block write to memory to continue. When clear, the ...
Page 165
... First AMD Athlon™ System Bus ID Reset Bits 15–8 First AMD Athlon™ System Bus ID (RO)—This field contains the ID of the first processor to read this register. Bits 7–0 Who Am I (RO)—This field returns the ID of the processor that accesses it. PCI Arbitration Control Register Bit 15 14 ...
Page 166
... SB Lock Disable (RW)—This bit controls the response of the AMD-751 system controller to a PCI request by the AMD-756 peripheral bus controller The AMD-751 ensures that all previous requests from the BIU and PCI are flushed out before granting the AMD-756 the PCI bus ...
Page 167
... Prefetch disabled (default Prefetch enabled Bit 1 PCI Prefetch Enable (RW)—This bit enables the AMD-751 to prefetch data from the SDRAM when a PCI master on the standard PCI bus reads from the main memory Prefetch disabled (default Prefetch enabled Bit 0 Park PCI (RW)— ...
Page 168
... Note: Enable APCI chaining and enable PCI chaining bits are available on the AMD-751 system controller Revision C and later. In previous revisions, these bits are read-only and always read 0. AGP VGA BIOS Mask Register ...
Page 169
... Bits 3–0 Processor Divider (RO)—This field contains the processor divider field supplied by the AMD Athlon system bus. Together with the CLK speed and the bus length fields, this field allows the AMD-751 system controller to properly program the AMD Athlon processor interface logic using the SIP protocol ...
Page 170
... Reserved for Dual Processor Implementation Bits 1–0 AMD Athlon™ System Bus Length (RO)—This field indicates the relative length of the AMD Athlon system bus trace routing on the motherboard. The default comes from bus pins AD[11:10 Short, non-AMD Athlon system bus design ...
Page 171
... Maximum Request Depth Reset Bits 31–24 Maximum Request Depth (always reads 0Fh)—The read-only value of 0Fh indicates that the AMD-751 system controller can handle a maximum of 16 AGP requests. Bits 23–10 Reserved (always reads 0) Bit 9 Sideband Address (always reads 1)—This bit is set to indicate that the AMD-751 supports sideband addressing. Bits 8– ...
Page 172
... AGP operations are accepted Bits 7–6 Reserved (always reads 0) Bit 5 4G_ENA (always reads 0)—When this bit indicates the address range four Gbytes. The AMD-751 system controller only supports 32-bit addressing. Bits 4–2 Reserved (always reads 0) Bits 1–0 Transfer Rate Select (RW)—One bit must be set in this field and the other cleared to indicate the desired AGP data transfer rate ...
Page 173
... Bit 7 Sync Enable (RW synchronization is guaranteed (default The AMD-751 system controller enables all writes to the GART range from processor to memory to be completed before initiating processor-to-AGP cycles, allowing synchronization between the processor and AGP Bits 6–0 Reserved (RW0)—These bits must remain 0 for proper operation. ...
Page 174
... When clear, AGP addresses that fall outside of the GART range do not cause probes (default When set, this bit forces AGP accesses that are not in the GART range to initiate AMD Athlon system bus probes to the processor(s) Bit 2 Reserved (RW0)—This bit is always set to 0 for proper operation. ...
Page 175
... SERR# Enable (RW)—This bit and bit 6 must be set report address parity errors. ASERR input to the AMD-751 system controller. The AMD-751 receives ASERR# in the AGP timing domain and passes it onto the PCI SERR# so that the AMD-756 peripheral bus controller may generate an interrupt. ...
Page 176
... AGP Initiator Access (RW)—This bit enables the AGP initiator (graphics controller) to access memory and the system PCI bus Disable master accesses from the APCI bus (default Enables the AMD-751 to accept master accesses from the APCI bus Bit 1 AGP Memory Space Enable (RW)—By default, the processor writes to graphics adapter memory on PCI bus 0 ...
Page 177
... Received Initiator Abort (RO)—This bit is set by a PCI initiator when its transaction is terminated with initiator abort PCI transactions proceeding normally 1 = The AMD-751 has detected that a transaction was terminated before completion Bit 12 Received Target Abort (RO)—The target issues a target abort when it detects a fatal error or cannot complete a transaction ...
Page 178
... MHz-Capable PCI Bus (always reads 1)—The APCI (AGP) interface supports 66-MHz operation. Bits 4–0 Reserved (always reads 0) AGP Revision ID Bit 7 6 Reset 0 0 Bits 7–0 AMD-751 System Controller Revision Code (RO)—00h = Revision A Programming Interface Bit 7 6 Reset 0 0 Bits 7–0 Programming Interface (always reads 0)—00h = Bridge Subclass Code Bit 7 ...
Page 179
... The bridge uses this field in conjunction with the secondary bus number register to determine when to respond to type 1 configuration transactions on the primary interface and to pass them on to the secondary interface. Chapter 7 AMD-751™ System Controller Data Sheet Header Type ...
Page 180
... Bits 7–4 I/O Limit Address Lower Nibble (RW)—These four bits determine A[15:12] of the upper boundary of the address range in which the AMD-751 system controller forwards I/O transactions from one interface to the other. A[31:16] are specified in Device 1, Offset 33h–32h (see page 169). ...
Page 181
... Received Initiator Abort (RWC)—This bit is set by an AGP initiator whenever its transaction is terminated with initiator abort AGP transactions proceeding normally 1 = The AMD-751, acting as a PCI initiator on the AGP bus, has terminated a transaction before completion Bit 12 Received Target Abort (RWC)—The target issues a target abort when it detects a fatal error or cannot complete a transaction by simultaneously deasserting DEVSEL# and asserting STOP# ...
Page 182
... AMD-751™ System Controller Data Sheet Bit 6 User-Defined Features (always reads 0)—The AMD-751 does not support user-defined features. Bit 5 66-MHz-Capable PCI Bus (always reads 1)—The maximum secondary PCI bus operating speed is 66 MHz. Bits 4–0 Reserved (always reads 0) Memory Base Reset ...
Page 183
... Offset 04, bit 0 is set). Chapter 7 Bits 15–4 Prefetchable Memory Base Bits 15–4 Prefetchable Memory Limit I/O Base Configuration Registers AMD-751™ System Controller Data Sheet Device 1 Offset 25h–24h Bits 3–0 Reserved Device 1 Offset 27h–26h Bits 3–0 Reserved Device 1 Offset 30h 2 1 Bit ...
Page 184
... AMD-751™ System Controller Data Sheet I/O Limit Bit 7 6 Reset 1 0 Bits 7–0 I/O Limit (RW)—This register defines the top address bits A[23:16 24-bit I/O limit address. Interrupt Control Bit Interrupt Pin Reset Bits 15–8 Interrupt Pin (RW) default 00h—This field indicates which interrupt pin the PCI-to-PCI bridge uses ...
Page 185
... Bit 4 Reserved (always reads 0) Bit 3 VGA Enable (RW)—When this bit is set, the AMD-751 system controller decodes and forwards VGA accesses to the secondary PCI bus rather than the primary PCI bus. VGA accesses include memory accesses in the range A0000–BFFFFh and I/O addresses in the ranges 3B0h–3BBh and 3C0– ...
Page 186
... SERR# assertions on the secondary bus are not forwarded to the primary bus (default SERR# assertions on the secondary bus are forwarded to the primary interface Bit 0 Parity Error Enable (always reads 0)—(Secondary bus) The AMD-751 system controller does not support parity checking. 172 Preliminary Information Configuration Registers 21910E— ...
Page 187
... Reserved (always reads 0) Bit 11 Enable Hang on Invalid GART Entries—This bit is used as a test mode to allow the AMD-751 system controller to hang on invalid GART entries. This bit is for software debug purposes only. For normal operation, do not set this bit. Note: The enable hang on invalid GART entries test mode is available on the AMD-751 system controller Revision C and later ...
Page 188
... GART cache has been enabled by software (see description of bit 2 below) Bit 9 Multiple Page Status (RO)—This bit is always 0 for the AMD-751 Revision C3 and later Variable number of pages per GART directory cache (GDC) entry are disabled. Each GDC entry cached refers to one 4-Kbyte page only. ...
Page 189
... AMD-751 Revision C3 and later. Note: Enable SB_SBA Detect Logic is available on the AMD-751 system controller Revision C3 and later. This newly defined control bit replaces a previously existing control in this register, “Multiple Pages Enabled”, which enabled multiple pages per GART entry ...
Page 190
... The bit is cleared when the update operation is completed. Bit 0 GART Cache Entry Invalidate (RW) (default 0)—Setting this bit forces the AMD-751 to invalidate the GART cache entry specified in bits [31:12] if they are present in the GART cache. The invalidate function is performed immediately following the write to this register. The bit is cleared when the invalidate operation is completed. Note: Bits 1– ...
Page 191
... When this bit is High, the system arbiter is disabled and the boot processor (given in WHAMI— Device 0, Offset 80— see page 151) has ownership of the system. AGP and PCI masters are not granted ownership of the bus. Chapter 7 AMD-751™ System Controller Data Sheet Bits 31–1 Reserved Configuration Registers BAR2 + Offset 04h–00h ...
Page 192
... AMD-751™ System Controller Data Sheet 178 Preliminary Information Configuration Registers 21910E—March 2000 Chapter 7 ...
Page 193
... Electrical Data 8.1 Absolute Ratings The AMD-751 system controller is not designed to operate beyond the parameters shown in Table 23. W ARNING Table 23. Absolute Ratings V DD REF_5V PIN V PIN V PIN V PIN T CASE T STORAGE Chapter 8 : The absolute ratings in Table 23 and associated conditions must be adhered to in order to avoid damage to the AMD-751 system controller and motherboard ...
Page 194
... AMD-751™ System Controller Data Sheet 8.2 Operating Ranges The AMD-751 system controller is designed to provide functional operation if the voltage and temperature parameters are within the limits defined in Table 24. Table 24. Operating Ranges Parameter REF_5V CASE Note: The voltage applied to V 180 Preliminary Information ...
Page 195
... DC Characteristics Table 25 shows the DC characteristics for the AMD-751 system controller. Table 26 on page 182 shows the DC characteristics for the AMD Athlon system bus/AMD-751. Table 25. DC Characteristics Symbol Parameter Description V Input Low Voltage (LVTTL Inputs Input High Voltage (LVTTL Inputs) ...
Page 196
... AMD-751™ System Controller Data Sheet Table 26. AMD Athlon™ System Bus/AMD-751™ System Controller DC Specification Symbol Parameter Description VccCore DC Supply Voltage V DC Input Reference Voltage REF I DC Reference Current VREF V (DC) DC Input High Voltage IH V (DC) DC Input Low Voltage IL V (AC) ...
Page 197
... Clock Control State Normal (Thermal Power) Halt-Disconnect 8.4.1 Thermal Considerations To al low for p rop ing int temperature specified in Table 23 on 179, the AMD-751 system controller requires a heatsink. Table 28 and Table 29 list recommended heatsinks and thermal materials, respectively. Table 28. Table 29. Chomerics Thermagon ...
Page 198
... AMD-751™ System Controller Data Sheet 184 Preliminary Information Electrical Data 21910E—March 2000 Chapter 8 ...
Page 199
... Switching Characteristics The AMD-751 system controller signal switching characteristics are presented in Tables 30 through 36. Valid delay, float, setup, and hold timing specifications are listed. All signal timings are based on the following conditions: The target signals are input or output signals that are switching from logical from logical ...
Page 200
... SYSCLK Switching Characteristics Table 30 contains the switching characteristics of the SYSCLK input to the AMD-751 system controller for 100-MHz processor bus operation. These timings are all measured with respect to the voltage levels indicated by Figure 31. Table 31 on page 187 contains the switching characteristics of the A_CLK input for 66-MHz PCI bus operation ...