AD1816AJS Analog Devices, AD1816AJS Datasheet
AD1816AJS
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AD1816AJS Summary of contents
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... All other trademarks are the property of their respective holders. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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AD1816A PRODUCT OVERVIEW The AD1816A SoundPort Controller is a single chip Plug and Play multimedia audio subsystem for concurrently processing multiple digital streams of 16-bit stereo audio in personal com- puters. The AD1816A maintains full legacy compatibility with applications written ...
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SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature Digital Supply ( Analog Supply ( Sample Rate ( Input Signal Frequency Audio Output Passband ANALOG INPUT Parameter Full-Scale Input Voltage (RMS ...
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AD1816A DIGITAL DECIMATION AND INTERPOLATION FILTERS* Parameter Audio Passband Audio Passband Ripple Audio Transition Band Audio Stopband Audio Stopband Rejection Audio Group Delay Group Delay Variation Over Passband ANALOG-TO-DIGITAL CONVERTERS Parameter Resolution Signal-to-Noise Ratio (SNR) (A-Weighted, Referenced to Full Scale) ...
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DIGITAL MIX ATTENUATORS* Parameter 2 2 Step Size (0 (1), Music, ISA Digital Mix Attenuation Range Span ANALOG OUTPUT Parameter Full-Scale Output Voltage (at L_OUT, R_OUT, PHONE_OUT) Output Impedance* External Load Impedance* Output Capacitance* External Load ...
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AD1816A (Guaranteed Over Operating Temperature Range) TIMING PARAMETERS Parameter IOW/IOR Strobe Width IOW/IOR Rising to IOW/IOR Falling Write Data Setup to IOW Rising IOW Falling to Valid Read Data AEN Setup to IOW/IOR Falling AEN Hold from IOW/IOR Rising Adr ...
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DRQ ( DRHD t DKSU DACK ( AESU AEN t STW IOR t RDDV PC_D [7:0] Figure 3. DMA Read Cycle DRQ ( DRHD t DKSU DACK ( ...
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... 0 +70 C Package +150 C PQFP TQFP Temperature Model Range AD1816AJS +70 C AD1816AJST + Plastic Quad Flatpack Thin Quad Flatpack. JST package option availability subject to 10,000 PC minimum order quantity. –8– – ( 35.1 C/W 7 C/W 28 C/W 35.3 C/W 8 C/W 27.3 C/W ORDERING GUIDE Package ...
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I S0_DATA/VOL_UP S0_LRCLK/VOL_DN S0_BCLK/GND 4 PC_A (15) PC_A (14 PC_A (13) PC_A (12) 7 PC_A (11) 8 PC_A (10 PC_A (9) PC_A ( PC_A (7) 13 ...
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AD1816A S0_BCLK/GND PIN 1 PC_A (15) 2 IDENTIFIER PC_A (14) 3 PC_A (13) 4 PC_A (12) 5 PC_A (11) 6 PC_A (10) 7 PC_A (9) 8 PC_A (8) 9 PC_A (7) 10 PC_A (6) 11 PC_A (5) ...
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Analog Signals (All Inputs must be AC-Coupled) Pin Name PQFP TQFP I/O MIC L_LINE R_LINE L_SYNTH R_SYNTH L_CD R_CD ...
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AD1816A Parallel Interface (All Outputs are 24 mA Drivers) Pin Name PQFP TQFP PC_D[7:0] 85–88, 91–94 83–86, 89–92 IRQ (x)* 75–81, 83 73–79, 81 DRQ (x) 72–74 70–72 PC_A[15:0] 4–19 2–17 AEN 20 18 DACK (x) 59–61 57–59 IOR 22 ...
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Muxed Serial Ports (8 mA Drivers) Pin Name PQFP TQFP 2 I S(0)_BCLK S(0)_LRCLK* 2 100 2 I S(0)_DATA S(1)_BCLK S(1)_LRCLK S(1)_DATA ...
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AD1816A Hardware Volume Pins Pin Name PQFP TQFP VOL_DN* 2, 99, 100 97, 98, 100 I VOL_UP 96, 99 Control Pins Pin Name PQFP TQFP XCTL0 PCLKO XCTL1 RING Power ...
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HOST INTERFACE The AD1816A contains all necessary ISA bus interface logic on chip. This logic includes address decoding for all onboard resources, control and signal interpretation, DMA selection and control logic, IRQ selection and control logic, and all interface configuration ...
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AD1816A Virtually all applications developed for SoundBlaster, Windows Sound System, AdLib and MIDI MPU-401 platforms run on the AD1816A SoundPort Controller. Follow the same development process for the controller as you would for these other devices. As the AD1816A contains ...
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SERIAL INTERFACES Serial Ports 2 The two I S serial ports on the AD1816A accept serial data in the following formats: Right-Justified, I Figure 9 shows the right-justified mode. LRCLK is HI for the left channel and ...
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... At start-up (after pin reset), there are exactly 12 time slots per frame. The frame rate will be 57,291 and 2/3 Hz (11 MHz sclk/ [16 bits 12 slots]). Interfacing with an Analog Devices 21xx family DSP can be achieved by putting the ADSP-21xx in 24 slot per frame mode, where the first 12 and second 12 slots in the ADSP-21xx frame are identical. ...
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SSPVI SS/SB Playback Substitution Data Input Valid Flag. This bit is ignored if: (1) Intercept mode is not enabled for SS/SB playback or (2) The AD1816A did not request data for SS/SB playback in the previous frame (see the SSPRQ ...
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AD1816A PNPR Plug and Play Reset flag. This bit is set by an AD1816A reset (RESETB pin asserted LOW Plug and Play reset command. This bit is cleared by the assertion of the FCLR bit in the ...
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Figure 14 illustrates the flexibility of the DSP Serial Port interface. This port can monitor or intercept any of the digital streams man- aged by the AD1816A. Any ADC or DAC data stream can be intercepted by the port, shipped ...
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... Plug and Play Device IDs (embedded in the logical device’s resource data) provide the system with the information required to find and load the correct device drivers. One custom driver, the AD1816A Sound System driver from Analog Devices, is required for cor- rect operation. In the other cases (MIDI, Game Port), the system can use generic drivers. Table III lists the AD1816A’s Logical Devices and compatible Plug and Play device drivers ...
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LDN PnP Function 0 I/O Port Address Descriptor (0x60-0x61) 0 I/O Port Address Descriptor (0x62-0x63) 0 I/O Port Address Descriptor (0x64-0x65) 0 Interrupt Request Level Select (0x70-0x71) 0 DMA Playback Channel Select (0x74) 0 DMA Capture Channel Select (0x75) 1 ...
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AD1816A [Base+0] Chip Status/Indirect Address 7 6 CRDY VBL INADR [5:0] (RW) Indirect Address for Sound System (SS). These bits are used to access the Indirect Registers shown in Table VIII. All registers data must be written in pairs, low ...
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PIO Debug RES PUR All bits in this register are sticky until any write that clears all bits to 0. ORL/ORR (RO) Overrange Left/Right detect. These bits record the largest output magnitude on the ADC right ...
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AD1816A [Base+6] PIO Data 7 6 PIO Playback/Capture [7:0] PIO Playback/ The Programmed I/O (PIO) Data Registers for capture and playback are mapped to the same address. Writes Capture [7:0] send data to the Playback Register and reads will receive ...
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IOR/IOW PC_D [7:0] ST FMT1 FMT0 C/L Format 0 000 Mono Linear, 8-Bit Unsigned 1 000 Stereo Linear, 8-Bit Unsigned 0 001 Mono -Law, 8-Bit Companded 1 001 Stereo -Law, 8-Bit Companded 0 010 Mono Linear 16-Bit Little Endian 1 ...
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AD1816A [Base+9] Capture Configuration RES CFMT [1:0] CEN (RW) Capture Enable. This bit enables or disables data capture. 0 Disable 1 Enable CIO (RW) Capture Programmed I/O. This bit determines whether the capture data is transferred via ...
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Joystick Position Data Low Byte 7 6 JAXIS [7:0] (RO) Joystick Axis Low Byte. Note: Axis to be read through this register is selected by the JSEL bits in the control register. A write to this register starts a ...
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AD1816A Table VII. Indirect Register Map and Reset/Default States Address Register Name 00 Low Byte TMP 01 Interrupt Enable and External Control 02 Voice Playback Sample Rate 03 Voice Capture Sample Rate 04 Voice Attenuation 05 FM Attenuation 2 06 ...
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Byte) ADDRESS (0x00) 01 (0x01) PIE CIE TIE VIE 02 (0x02) VPSR [15.8] 03 (0x03) VCSR [15:8] 04 (0x04) LVM RES 05 (0x05) LFMM RES 06 (0x06) LS1M RES 07 (0x07) LS0M RES 08 ...
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AD1816A RIE RW Ring Interrupt Enable; 0 Ring Interrupt disabled 1 Ring Interrupt enabled DIE RW DSP Interrupt Enable; 0 DSP Interrupt disabled 1 DSP Interrupt enabled VIE RW Volume Interrupt Enable. If enabled, software increments/decrements BUTTON MODIFIER via interrupt ...
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RS1M Right I S(1) Mute Unmuted Muted. 2 LS1A [5:0] Left I S(1) Attenuation register. The LSB represents –1.5 dB, 000000 = 0 dB and the range –94.5 dB. 2 LS1M ...
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AD1816A [13] TIMER CURRENT COUNT TCC [15:8] TCC [15:0] Timer DMA Current Count register. Contains the current timer count. Reading and Writing must be done when TE is deasserted. [14] MASTER VOLUME ATTENUATION 7 6 ...
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MIC/PHONE IN GAIN/ATTENUATION MCM M20 RES PIA [3:0] PHONE_IN Attenuation. The LSB represents –3 dB, 0000 = 0 dB and the range –45 dB. PIM PHONE_IN Mute. MCA [4:0] ...
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AD1816A [33] DSP CONFIGURATION DS1 DS0 DIT RES DFS [2:0] DSP Frame Sync Source. Sets the DSP Port Frame Sync according to the following source. 000—Maximum Frame Rate 2 001—I S(0) Sample Rate 2 010—I ...
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POM PHONE-OUT Mute Unmuted Muted. 3DD [3:0] 3D Depth Phat Stereo Enhancement Control. The LSB represents 6 2/3% phase expansion, 0000 = 0% and the range 100%. 3DDM 3D Depth Mute. Writing a ...
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AD1816A DM DAC Mute. This bit mutes the digital DAC output entering the analog mixer. GPSP Game Port Speed Select. Selects the operating speed of the game port. 0 Slow Game Port 1 Fast Game Port PD3D Power-Down 3D. Turns ...
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Register Name Music0: Address (w), Status (r) Music0: Data (w) Music1: Address (w) Music1: Data (w) MPU-401 Registers The AD1816A contains a set of ISA Bus registers (ports) that correspond to those used by the ISA bus MIDI audio interface ...
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... Note: All addresses are depicted in hexadecimal notation. Vendor ID: ADS7181 Serial Number: FFFFFFFF Checksum: 2F PNP Version: 1.0, vendor version: 20 ASCII string: “Analog Devices AD1816A” Logical Device ID: ADS7180 not a boot device, implements PNP register(s) 31 Start dependent function, best config IRQ: channel( type(s) active-high, edge-triggered ...
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PLUG AND PLAY KEY AND “ALTERNATE KEY” SEQUENCES One additional feature of the AD1816A is an alternate programming method used, for example BIOS wants to assume control of the AD1816A and present DEVNODES to the OS (rather than ...
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AD1816A AD1816 AND AD1816A COMPATIBILITY The AD1816 and AD1816A are pin for pin and functionally compatible. The AD1816A may be dropped directly into an existing AD1816 design. However, the AD1816A has greater pin assignment flexibility to accommodate a wider range ...
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AD1816A FLAG BYTES The AD1816A has four flag bytes that are used as shown below: (*) AD1816-compatible setting. Byte MODEM_EN Program to one to enable the modem logical device. This logical device has ...
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AD1816A Byte IRQSEL4 9 11 IRQSEL9 14 IRQSEL11 — — — XTRASZ0[3:0] Sets the XTRA device I/O range 0 length. The XTRASZ0 bits set the length of the first XTRA device I/O range as follows: XTRASZ0 0000 ...
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MAPPING THE AD1816 EEPROM INTO THE AD1816A EEPROM The equations below map AD1816 flags onto AD1816A flags: MODEM_EN = MODEM_EN XTRA_EN = XTRA_EN SUPER_EN = 0 2 S0_HV = VOL_EN * VOL_SEL I XTRA_HV = VOL_EN * VOL_SEL IRQSEL12_13 = ...
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AD1816A PQFP TQFP Pin Function S0_DATA VOL_UP 2 2 100 I S0_LRCLK VOL_DN S0_BCLK GND 68 66 XCTL0/PCLKO PNPRST 69 67 XCTL1/RING LD_SEL1 75 73 IRQ(15) IRQ(11 IRQ(11) IRQ(9) IRQ(4) ...
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... You can skip over bytes that you don’t care to write by just performing a ROM read instead of a ROM write followed by a ROM read. REFERENCE DESIGNS AND DEVICE DRIVERS Reference designs and device drivers for the AD1816A are available via the Analog Devices Home Page on the World Wide Web at http://www.analog.com. Reference designs may also be obtained by contacting your local Analog Devices Sales representative or authorized distributor ...
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... MIC L_LINE R_LINE L_SYNTH R_SYNTH L_CD R_CD L_VID R_VID AD1816AJS PHONE_IN L_OUT R_OUT PHONE_OUT CX3D RX3D V REF_X V REF L_FILT R_FILT L_AAFILT R_AAFILT GNDA GND GND GND GND GND LOCATION OF THIS PIN IS DETERMINED BY THE EEPROM Figure 16. Recommended Application Circuit – ...
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S a. ADC Audio 0 –0.1 –0.2 0 0.1 0 ADC Audio Passband Figure 17. AD1816A Frequency ...
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AD1816A 0.037 (0.95) 0.026 (0.65) SEATING 0.004 (0.10) 0.010 (0.25) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 100-Lead Plastic Quad Flatpack (S-100) 0.923 (23.45) 0.903 (22.95) 0.096 0.791 (20.10) (2.45) 0.783 (19.90) MAX 0.742 (18.85) TYP 80 81 PLANE ...
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