IDT723614 Integrated Device Technology, Inc., IDT723614 Datasheet

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... Register Parity Gen/Check AEA AFA , , and flags synchronized by CLKA AEB AFB , , and flags synchronized by CLKB MBF1 PEFB Parity PGB 36 EFB AEB FFB AFB Write 36 CLKB CSB Port-B R Control W/ B Logic ENB BE SIZ0 SIZ1 SW0 SW1 3146 drw 01 IDT723614 35 MAY 1997 DSC-3146/4 1 ...

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... Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths. The IDT723614 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous (free-running) port clock by enable signals ...

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... The empty flag ( AEA AEB empty ( , ) flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT723614 is characterized for operation from AFA AFB , ) TQFP (PN120-1, order code: PF) TOP VIEW COMMERCIAL TEMPERATURE RANGE ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING PIN DESCRIPTION Symbol Name A0-A35 Port A Data AEA Port A Almost-Empty Flag (Port A) the number of 36-bit words in FIFO2 is less than or equal to the value in AEB Port B Almost-Empty Flag (Port B) number of 36-bit words in FIFO1 is less than or equal to the value in the ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING PIN DESCRIPTION (CONTINUED) Symbol Name `FS1, FS0 Flag-Offset Selects MBA Port A Mailbox Select MBF1 Mail1 Register Flag MBF2 Mail2 Register Flag ODD/ Odd/Even Parity EVEN Select PEFA Port A Parity Error Flag (Port A) organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant ...

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... Port B Write/Read Select SIGNAL DESCRIPTIONS RESET The IDT723614 is reset by taking the reset ( LOW for at least four port A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH transitions. The reset input can switch asynchronously to the clocks. A device reset initializes the internal read and write pointers of each FIFO and forces the ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING clock that reads data from the FIFO have not elapsed since the time the word was written. The empty flag of the FIFO is set HIGH by the second LOW-to-HIGH transition of the synchro- nizing clock, and the new data word can be read to the FIFO output register in the following cycle ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING AEA AEA AEB AEB ALMOST EMPTY FLAGS ( , The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an almost-empty flag monitors a write-pointer and a read-pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2 ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I (2) V Output Voltage Range O I Input Clamp Current Output Clamp Current Continuous Output Current, (V ...

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... Only applies for a clock edge that does a FIFO read. 2. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timimg constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. IDT723614L15 IDT723614L20 IDT723614L30 Min. – ...

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... Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. 3. Only applies when a new port B bus size is implemented by the rising CLKB edge. 4. Only applies when reading data from a mail register. = 30pF (See Figures 4 through 26) L IDT723614L15 IDT723614L20 IDT723614L30 Min. 2 FFA and 2 EFA ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING BYTE ORDER ON PORT SIZ1 SIZ0 SIZ1 SIZ0 SIZ1 SIZ0 SIZ1 SIZ0 A35—A27 A26—A18 A17— B35—B27 B26—B18 B17— (a) LONG WORD SIZE B35—B27 B26—B18 B17—B9 ...

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... CLKB according to Figure 1. Only 36-bit long-word data is written to or read from the two FIFO memories on the IDT723614. Bus-matching opera- tions are done after data is read from the FIFO1 RAM and before data is written to the FIFO2 RAM. Port B bus sizing does not apply to mail register operations ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING PORT-B MAIL REGISTER ACCESS In addition to selecting port-B bus sizes for FIFO reads and writes, the port B bus size select (SIZ0, SIZ1) inputs also access the mail registers. When both SIZ0 and SIZ1 are ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING SW1 SW0 SW1 SW0 L H SW1 SW0 H L SW1 SW0 H H Figure 3. Byte Swapping (Long Word Size Example) A35—A27 A26—A18 A17— B35—B27 B26—B18 B17—B9 (a) NO SWAP A35— ...

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... B0-B35 inputs. PARITY GENERATION A HIGH level on the port A parity generate select (PGA) or port B parity generate select (PGB) enables the IDT723614 to generate parity bits for port reads from a FIFO or mailbox register. Port A bytes are arranged as A0-A8, A9-A17, A18- 26, and A27-A35, with the most significant bit of each byte used as the parity bit ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKA CLKB t RSTS RST FS1,FS0 FFA EFA FFB EFB t RSF MBF1 , MBF2 AEA AFA AEB AFB Figure 4. Device Reset Loading the X Register with the Value of Eight t RSTH t FSS 0,1 t WFF t REF t WFF ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKA FFA HIGH t ENS CSA t ENS ENS MBA t ENS ENA A35 ODD/ EVEN PEFA NOTE: 1. Written to FIFO1. t ENH t ENH t ENH t ENH t ENS t DH (1) ( PDPE Valid Figure 5. Port-A Write Cycle Timing for FIFO1 ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKB FFB HIGH CSB ENB SW1, SW0 t t SZS SZH SZS SZH SIZ1, (0,0) SIZ0 B0-B35 ODD/ EVEN PEFB NOTE: 1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2 ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKB FFB HIGH CSB ENB SW1, SW0 t SZS t SZH SZH SZS SIZ1, SIZ0 (0, 1) Little B0-B17 Endian Big Endian B18-B35 EVEN ODD/ PEFB NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register. ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKB FFB HIGH t ENS CSB t ENS ENS ENB t SWS SW1, SW0 t SZS t t SZH SZS SZS SZS SZH SIZ1, (1,0) SIZ0 t DS Little B0- Endian Big B27- Endian B35 ODD/EVEN PEFB NOTES: 1. SIZ0 = HIGH amd SIZ1 = HIGH writes data to the mail2 register. ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING DATA SWAP TABLE FOR BYTE WRITES TO FIFO2 SWAP MODE WRITE NO. SW1 SW0 Figure 8. Port-B Byte Write Cycle Timing for FIFO2 (continued) DATA WRITTEN TO FIFO2 BIG LITTLE ENDIAN ENDIAN B35-B27 B8-80 A35-A27 COMMERCIAL TEMPERATURE RANGE ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKB EFB HIGH CSB ENB SW1, SW0 t t SZS SZH SZS SZH SIZ1, (0,0) NOT (1,1) SIZ0 PGB, ODD/ EVEN t EN B0-B35 NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKB EFB HIGH CSB ENB SW1, SW0 t SZS t SZH SZS SZH SIZ1, (0,1) NOT (1,1) SIZ0 PGB, ODD/ EVEN t EN Little (2) B0-B17 Endian Big (2) B18-B35 Endian NOTES: 1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35. ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKB EFB HIGH CSB ENS ENB t SWS SW1, SW0 t t SZH SZS SZS SZH SIZ1, (1,0) (1,0) SIZ0 (1) Not (1,1) t PGS PGB, ODD/ EVEN t EN Previous Data B0-B8 B27-B35 Previous Data NOTES: 1 ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKA EFA HIGH CSA MBA ENA t MDV A35 t PGS PGA, ODD/ EVEN NOTE: 1. Read from FIFO2.. t ENH t ENS t ENS t A (1) Previous Data Word 1 t PGS t PGH Figure 12. Port-A Read Cycle Timing for FIFO2 ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKA CSA LOW HIGH t ENS MBA t ENS ENA FFA HIGH A35 W1 t SKEW1 CLKB EFB FIFO1 Empty CSB LOW R LOW W/ B SIZ1, LOW SIZ0 ENB B0 -B35 NOTES the minimum time between a rising CLKA edge and a rising CLKB edge for ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKB CSB LOW HIGH t ENS SIZ1, SIZ0 t ENS ENB FFB HIGH B35 W1 t SKEW1 CLKA EFA FIFO2 Empty CSA LOW R LOW W/ A LOW MBA ENA A0 -A35 NOTES the minimum time between a rising CLKB edge and a rising CLKA edge for ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKB CSB LOW LOW SIZ1, LOW SIZ0 t ENS ENB EFB HIGH B0 - B35 Previous Word in FIFO1 Output Register CLKA FFA FIFO1 Full CSA LOW R HIGH W A MBA ENA A0 - A35 NOTES: 1 ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLK t t CLKH CLKL CLKA CSA LOW R LOW W/ A MBA LOW t ENS ENA EFA HIGH A0 - A35 Previous Word in FIFO2 Output Register CLKB FFB FIFO2 Full CSB LOW R HIGH W B SIZ1, SIZ0 ENB ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKA t t ENS ENA t CLKB AEB X Long Word in FIFO1 ENB NOTES the minimum time between a rising CLKA edge and a rising CLKB edge for SKEW2 between the rising CLKA edge and rising CLKB edge is less than t ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKA t ENS ENA AFA [64-(X+1)] Long Words in FIFO1 CLKB ENB NOTES the minimum time between a rising CLKA edge and a rising CLKB edge for SKEW2 between the rising CLKA edge and rising CLKB edge is less than t ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKA t ENS CSA MBA ENA A0 - A35 CLKB MBF1 CSB SIZ1, SIZ0 ENB B35 FIFO1 Output Register NOTE: 1. Port B parity generation off (PGB = LOW). Figure 21. Timing for Mail1 Register and t ENH PMF t MDV ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING CLKB CSB SIZ1, SIZ0 ENB B0 - B35 CLKA MBF2 CSA MBA ENA A35 FIFO2 Output Register NOTE: 1. Port-A parity generation off (PGA = LOW). t ENH t ENS t t SZS SZH PMF t MDV t PMR W1 (Remains valid in Mail2 Register after read) Figure 22 ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING ODD/ EVEN MBA PGA t POPE PEFA Valid Figure 23. ODD/ ODD/ EVEN SIZ1, SIZ0 PGB t PEFB Valid Figure 24. ODD/ t POPE Valid Valid EVEN EVEN MBA, and PGA to t POPE POPE Valid Valid EVEN ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING ODD/ EVEN CSA LOW MBA PGA t EN A8, A17, A26, A35 NOTE: 1. ENA is HIGH. Figure 25. Parity Generation Timing when Reading from the Mail2 Register ODD/ EVEN CSB LOW SIZ1, SIZ0 PGB t EN B8, B17, ...

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... Figure 27 was taken while simultaneously reading and writing the FIFO on the CC(f) IDT723614 with CLKA and CLKB set to fs. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load. ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PZL t PLZ Low-Level Output t PZH High-Level Output t PHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTE: 1 ...

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... IDT723614 CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING ORDERING INFORMATION IDT 723614 X Device Type Power Speed Package Process/ Temperature Range COMMERCIAL TEMPERATURE RANGE BLANK Commercial ( + Thin Quad Flat Pack (TQFP, PN120-1) PQF Plastic Quad Flat Pack (PQFP, PQ132-1) 15 Commercial Only ...