ST10R272 STMicroelectronics, ST10R272 Datasheet
ST10R272
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ST10R272 Summary of contents
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... Fail Safe Protection Programmable watchdog timer Oscillator Watchdog Interrupt 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (PEC) 16-priority-level interrupt system with 17 sources, sample-rate down March 2001 ST10R272L Dedicated P.6 P.4 pins XSSP OSC WDT PLL ST10 CORE DPRAM ...
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PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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P4.3/A19 P4.4/A20/SSPCE1 P4.5/A21/SSPCE0 P4.6/A22/SSPDAT P4.7/A23/SSPCLK RD W R/W RL READY/READY ALE RPD P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 P5.12/T6IN P5.11/T5EUD P5.10/T6EUD P7.3/POUT3 P7.2 P7.1 P7.0 ...
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... To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Observe minimum and maximum high/low and rise/fall times specified in the AC Characteristics. Table 1 Pin definitions ST10R272L - PIN DESCRIPTION GPT2 Timer T6 Ext.Up/Down Ctrl.Input GPT2 Timer T5 Ext.Up/Down Ctrl.Input GPT2 Timer T6 Count Input GPT2 Timer T5 Count Input GPT1 Timer T4 Ext ...
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... ST10R272L - PIN DESCRIPTION P3.0 – 8-21 I/O P3.13 P3. 15-bit (P3.14 is missing) bidirectional I/O port. Port 3 is bit- wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high- 5T impedance state. Port 3 outputs can be configured as push/ pull or open drain drivers ...
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... Polarity is programmable. Table 1 Pin definitions ST10R272L - PIN DESCRIPTION Least Significant Segment Addr. Line ... Segment Address Line Segment Address Line ...
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... External Access Enable pin. Low level at this pin during and after reset forces the ST10R272L to begin instruction execu- tion out of external memory. A high level forces execution out of the internal ROM. The ST10R272L must have this pin tied to ‘0’. 5T PORT0 has two 8-bit bidirectional I/O ports P0L and P0H bit-wise programmable for input or output via direction bits ...
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... P6.4 CS4 5T P6.5 HOLD 5T P6.6 HLDA 5T P6.7 BREQ Table 1 Pin definitions ST10R272L - PIN DESCRIPTION V SS Chip Select 0 Output ... Chip Select 4 Output External Master Hold Request Input (Master mode: O, Slave mode: I) Hold Acknowledge Output Bus Request Output With . 9/77 1 ...
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... ST10R272L - PIN DESCRIPTION P2.8 – I/O P2. ... ... 93 I P7.0 – I/O P7 RPD 38, 49 39, 50, 70 The following I/O kinds are used. page 40 for a detailed description. PO: Power pin 3T tolerant pin (voltage max. respect to Vss is -0.5 to VDD + 0.5) 5V tolerant pin (voltage max. respect to Vss is -0.5 to 5.5 only if chip is powered) 5S tolerant and fail-safe pin (-0 ...
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... FUNCTIONAL DESCRIPTION ST10R272L architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram overviews the different on- chip components and the internal bus structure. EA, ALE, RD, WR/WRL, READY, NMI, RSTIN, RSTOUT dedicated pins XTAL1 OSC XTAL2 ...
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... ST10R272L - MEMORY MAPPING 3 MEMORY MAPPING The ST10R272L is a ROMless device, the internal RAM space is 1 KByte. The RAM address space is used for variables, register banks, the system stack, the PEC pointers (in 00’FCE0h - 00’FCFFh) and the bit-addressable space (in 00’FD00h - 00’FDFFh). ...
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... SP STKOV STKUN Exec. Unit Instr. Ptr Instr. Reg 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs ST10R272L - CENTRAL PROCESSING UNIT CPU MDH R15 MDL Mul./Div.-HW Bit-Mask Gen. General Purpose ALU Registers 16-Bit Barrel-Shift Context Ptr R0 ADDRSEL 1 IDX1 ...
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... ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) 5 MULTIPLY-ACCUMULATE UNIT (MAC) The MAC is a specialized co-processor added to the ST10R272L CPU core to improve the performance of signal processing algorithms. It includes: • a multiply-accumulate unit • an address generation unit, able to feed the mac unit with 2 operands per cycle • ...
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... Three 16-bit status and control registers: MSW: MAC Status Word, MCW: MAC Control Word, MRW: MAC Repeat Word. Program control • Repeat Unit allows some MAC co-processor instructions to be repeated up to 8192 times. Repeated instructions may be interrupted. • MAC interrupt (Class B Trap) on MAC condition flags. ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) 15/77 1 ...
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... ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) 5.2 MAC Operation Instruction pipelining All MAC instructions use the 4-stage pipeline. During each stage the following tasks are performed: • FETCH: All new instructions are double-word instructions. • DECODE: If required, operand addresses are calculated and the resulting operands are fetched. IDX and GPR pointers are post-modified if necessary. • ...
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... CoMACM [IDX +],... i CoMACM [IDX -],... i CoMACM [IDX +QX ],... i j CoMACM [IDX -QX ],... i j Table 3 Parallel data move addressing ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) Mnemonic Address Pointer Operation [IDX i ] (IDX i ) (IDX i ) (no-op) [IDX i ] (IDX i ) (IDX (i=0,1) [IDX i -] (IDX i ) (IDX (i=0,1) [IDX (IDX i ) (IDX ( (i, j =0,1) [IDX ...
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... ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) The Parallel Data Move shifts a table of operands in parallel with a computation on those operands. Its specific use is for signal processing algorithms like filter computation. The following figure gives an example of Parallel Data Move with CoMACM instruction. 16-bit n n-2 n-4 Before Execution ...
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... Register E bit x 0 MAS 1 MAS 1 Note In this case, the accumulator and the status register are not affected. MAS readable from a CoSTORE instruction. ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) N bit Output of the Limiter x unchanged 0 7fffh 1 8000h Table 4 Data Limit Values 19/77 1 ...
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... ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) Accumulator shifter The Accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The source operand of the shifter is the Accumulator and the possible shifting operations are: • No shift (Unmodified) • 8-bit Arithmetic Left Shift • 8-bit Arithmetic Right Shift E, SV and SL bits from MSW are affected by Left shifts, therefore if the saturation mechanism is enabled (MS), the behavior is similar to the one of the arithmetic unit ...
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... Note that the IP value stacked after a MAC interrupt does not point to the instruction that triggers the interrupt. N FETCH N-1 DECODE N-2 EXECUTE N-3 WRITEBACK Figure 7 Pipeline diagram for MAC interrupt response time ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) Response Time N+1 N+2 N+3 N N+1 N+2 N-1 N N+1 ...
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... When this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. PEC services are very well suited, for example, to the transmission or reception of blocks of data. The ST10R272L has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities. ...
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... GPT2 CAPREL Register ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error PWM Channel 3 SSP Interrupt PLL Unlock Table 5 List of possible interrupt sources, flags, vector and trap numbers ST10R272L - INTERRUPT AND TRAP FUNCTIONS Request Enable Interrupt Flag Flag Vector CC8IR CC8IE ...
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... ST10R272L - INTERRUPT AND TRAP FUNCTIONS 6.2 Hardware Traps Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware traps cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR) ...
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... PARALLEL PORTS The ST10R272L provides I/O lines organized into 7 input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs by direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation by control registers ...
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... ST10R272L - PWM MODULE of external memory space, the address space can be restricted to 1 MByte, 256 KByte KByte. 9 PWM MODULE A 1-channel Pulse Width Modulation (PWM) Module operates on channel 3. The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre- aligned PWM ...
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... T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. ST10R272L - GENERAL PURPOSE TIMERS 27/77 1 ...
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... ST10R272L - GENERAL PURPOSE TIMERS Timer input selection F =50MHz CPU 000b 001b Prescaler 8 16 Factor Input 6.25 MHz 3.125 Frequency MHz Resolution 160ns 320ns Period 10.49ms 20.97ms Table 8 GPT1 timer input frequencies, resolution and periods T2E Clock n 2 n=3...10 T2IN CPU C lock ...
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... Prescaler 4 8 Factor Input 12.5 MHz 6.25 MHz 3.125 Frequency Resolution 80ns 160ns Period 5.24ms 10.49ms Table 9 GPT2 timer input frequencies, resolution and periods ST10R272L - GENERAL PURPOSE TIMERS 010b 011b 100b 1.563 781 MHz MHz KHz 320ns 640ns 1.28 us 20.97ms 41.94ms 83 ...
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... ST10R272L - SERIAL CHANNELS T5EUD CPU Clock n 2 n=2...9 T5IN CAPIN T6IN CPU Clock n 2 n=2...9 T6EUD 11 SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP). ...
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... H H 028A / 028B 2400 H H 0515 / 0516 1200 H H 0A2B / 0A2C 600 H H 1FFF / 1FFF 127 ST10R272L - SERIAL CHANNELS = 50MHz CPU Deviation Error Reload Value 0.0% / 0.0% 0000 / 0000 H +3.3% / -2.1% 0011 / 0012 H +0.5% / -3.1% 001A / 001B H +0.5% /-1.4% 0035 / 0036 H +0 ...
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... ST10R272L - WATCHDOG TIMER SSPCKS Value 011 SSP clock = CPU clock divided by 16 100 SSP clock = CPU clock divided by 32 101 SSP clock = CPU clock divided by 64 110 SSP clock = CPU clock divided by 128 111 SSP clock = CPU clock divided by 256 Table 11 Synchronous baud rate and SSPCKS reload values ...
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... When READY is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. Then the internal reset sequence is started. The watchdog reset cannot occur while the ST10R272L is in bootstrap loader mode. Bidirectional reset: The bidirectional reset is activated by setting bit BDRSTEN (bit 3 in SYSCON register) ...
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... SPECIAL FUNCTION REGISTERS The following table lists all ST10R272L SFRs in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. ...
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... IDMANUF F07Eh E IDMEM F07Ah E IDPROG F078h E IDX0 b FF08h Table 13 Special functional registers ST10R272L - SPECIAL FUNCTION REGISTERS 8-Bit Description Address C5h EX1IN Interrupt Control Register C6h EX2IN Interrupt Control Register C7h EX3IN Interrupt Control Register 08h CPU Context Pointer Register B5h GPT2 CAPREL Interrupt Control Register ...
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... ST10R272L - SPECIAL FUNCTION REGISTERS Physical Name Address IDX1 b FF0Ah MAH FE5Eh MAL FE5Ch MCW FFDCh MDC b FF0Eh MDH FE0Ch MDL FE0Eh MRW b FFDAh MSW b FFDEh ODP2 b F1C2h E ODP3 b F1C6h E ODP6 b F1CEh E ODP7 b F1D2h E ONES FF1Eh P0L b FF00h P0H b FF02h P1L b FF04h ...
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... S0RIC b FF6Eh S0TBIC b F19Ch E S0TBUF FEB0h S0TIC b FF6Ch Table 13 Special functional registers ST10R272L - SPECIAL FUNCTION REGISTERS 8-Bit Description Address 62h PEC Channel 2 Control Register 63h PEC Channel 3 Control Register 64h PEC Channel 4 Control Register 65h PEC Channel 5 Control Register 66h PEC Channel 6 Control Register ...
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... ST10R272L - SPECIAL FUNCTION REGISTERS Physical Name Address SP FE12h SSPCON0 EF00h X SSPCON1 EF02h X SSPRTB EF04h X SSPTBH EF06h X STKOV FE14h STKUN FE16h SYSCON b FF12h T2 FE40h T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b FF44h T4IC b FF64h T5 FE46h T5CON b FF46h T5IC ...
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... F19Eh E ZEROS b FF1Ch Note 1. The system configuration is selected during reset. Note 2. Bit WDTR indicates a watchdog timer triggered reset. ST10R272L - SPECIAL FUNCTION REGISTERS 8-Bit Description Address C7h SSP Interrupt Control Register CFh PLL unlock Interrupt Control Register 8Eh Constant Value 0’s Register (read only) ...
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... Absolute Maximum Ratings. SS The parameters listed in this section represent both the ST10R272L controller characteristics and the system requirements. To aid parameters interpretation in design evaluation, the a symbol column is marked: CC for Controller Characteristics: The ST10R272L logic provides signals with the ...
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... Acceptable • 6V transient signals on 5V tolerant (5T) pin on the non powered chip: ...NOT Acceptable • 6V transient signals on 5V fail-safe (5S) pin on the non powered chip:.......... Acceptable ST10R272L - ELECTRICAL CHARACTERISTICS )= + 41/77 1 ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS 16.2 DC Characteristics V = 3.3V 0. Parameter Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN, RPD Input high voltage XTAL1 Output low voltage (ALE, RD, WR, BHE, CLKOUT, , RSTIN,RSTOUT CSX) Output low voltage (all other outputs) ...
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... memory (16-bit demux bus mode, no waitstates, no memory tri-state waitstates, normal ALE). 8) Typical value at 25° µA. 9) This parameter is tested including leakage currents. All inputs (including pins configured as inputs 0 figured as outputs) disconnected. ST10R272L - ELECTRICAL CHARACTERISTICS Limit Values Symbol min. 4 – I P0H 5 ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS 200 150 100 15 10 Figure 10 Supply/idle current vs operating frequency 44/ CCmax I IDmax 50 f [MHz] CPU ...
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... Input timing reference levels: ................................................................................. +1.5 V • Output timing reference levels: .............................................................................. +1.5 V • Output load: ................................................................................................. see Figure 1.5V 10 2.5ns From output under test Figure 12 Output load circuit waveform ST10R272L - ELECTRICAL CHARACTERISTICS 90% timing ref. points Figure 11 Input waveforms ~ C = 50pF L 1.5V timing reference points 90% 1.5V 10% 2 1mA ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS From output under test LOAD V OL For timing purposes a port pin is no longer floating when a 150 mV change from load voltage occurs, but begins to float when a 150 mV change from the loaded VOH/VOL level occurs for floating measurements only. 46/77 ...
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... CPU Clock Generation Mechanisms ST10R272L internal operation is controlled by the CPU clock f clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external timing (AC Characteristics) specification therefore depends on the time between two consec- utive edges of the CPU clock, called “TCL” (see figure below). ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS P0.15-13 (P0H.7- Table 15 CPU clock generation mechanisms 1) The maximum depends on the duty cycle of the external clock signal. The maxi- mum input frequency is 25 MHz when using an external crystal oscillator, but higher frequencies can be applied with an external clock source. ...
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... The relative deviation for periods of more than one TCL is lower than for one single TCL. For a period TCL the minimum value is computed using the corresponding deviation ST10R272L - ELECTRICAL CHARACTERISTICS instead of DC TCL max min the PLL circuit synchronizes the CPU clock to the input clock ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS where N = number of consecutive TCLs and 1 and 3TCL min PLL jitter is an important factor for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. ...
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... The timing tables below use three variables derived from the BUSCONx registers and represent programmed memory cycle characteristics. Table 16 describes how these variables are computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time ST10R272L - ELECTRICAL CHARACTERISTICS Symbol Values t TCL * <ALECTL> 2TCL * (15 - < ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS 16.3.3 Multiplexed Bus 3 ALE cycle time = 6 TCL + 2 A Parameter Symbol ALE high time t 5 Address (P1, P4), BHE t 6 setup to ALE Address (P0) setup to ALE t 6m Address hold after ALE t 7 ALE falling edge to RD (with RW-delay) ALE falling edge to RD, ...
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... RD, WR ALE fall. edge to RdCS WrCS (with RW delay) ALE fall. edge to RdCS WrCS (no RW delay) t Address float after RdCS 44 1 (with RW delay) Address float after RdCS (no RW delay) ST10R272L - ELECTRICAL CHARACTERISTICS Max. CPU Clock = 50 MHz min. max – SR – – – ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS Parameter Symbol RdCS to Valid Data (with RW delay) RdCS to Valid Data (no RW delay) RdCS, WrCS Low Time t 48 (with RW delay) RdCS, WrCS Low Time t 49 (no RW delay) Data valid to WrCS t 50 Data hold after RdCS Data float after RdCS ...
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... CLKOUT t 5 ALE t 38u CSx t 6 A23-A16 (A15-A8) BHE t 6m Read Cycle BUS P0 RD Write Cycle BUS P0 WR, WRL, WRH Figure 16 External memory cycle: multiplexed bus, with/without read/write delay, normal ALE ST10R272L - ELECTRICAL CHARACTERISTICS 39u Address Address Data Address Data Out ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS CLKOUT t 5 ALE t 38u CSx t 6d/b A23-A16 (A15-A8) BHE Read Cycle t 6m BUS P0 RD Write Cycle BUS P0 WR WRL, WRH multiplexed bus, with/without read/write delay, extended ALE 56/ 39u Address t 7 Address Address Figure 17 External memory cycle 40u t 27 ...
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... CLKOUT t 5 ALE t 6b/d A23-A16 (A15-A8) BHE t 6m Read Cycle BUS P0 RdCSx Write Cycle BUS P0 WrCSx multiplexed bus, with/without read/write delay, normal ALE, read/write chip select ST10R272L - ELECTRICAL CHARACTERISTICS Address Address Data Address Data Out Figure 18 External memory cycle Address t 52m ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS CLKOUT t ALE t 6d/b A23-A16 (A15-A8) BHE Read Cycle t BUS P0 RdCSx Write Cycle BUS P0 WR WRL, WRH multiplexed bus, with/without read/write delay, extended ale, read/write chip select 58/ Address Address Address Figure 19 External memory cycle Data 19m Data Out ...
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... ALE low to valid data in Address to valid data in Data hold after RD rising edge Data float after RD rising 1) 2) edge (with RW-delay) Data float after RD rising 1 2 edge (no RW-delay) Data valid to WR ST10R272L - ELECTRICAL CHARACTERISTICS T = -40 to +85 ° ( MHz CPU clock without waitstates) C ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS Parameter Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR Address hold after WRH Latched CS setup to ALE Unlatched CS setup to ALE Latched CS low to Valid Data In Unlatched CS low to Valid Data In Latched CS hold after RD, WR Unlatched CS hold after RD, ...
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... If the following bus cycle is a muxtiplexed bus A cycle, refer to equivalent multiplexed AC timing (which are still applicable due to automatic insertion an idle state (2TCL) when switching from Demultiplexed to Multiplexed Bus Mode. ST10R272L - ELECTRICAL CHARACTERISTICS Max CPU Clock 50MHz min. max. ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS CLKOUT ALE CSx A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RD Write Cycle P0 BUS (D15-D8) D7-D0 WR(L), WRH demultiplexed bus, with/without read/write delay, normal ALE 62/ 38u 39u Address Data Out Figure 20 External memory cycle 41u t t 28, 28h t 18 ...
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... CLKOUT t 5 ALE t 38u CSx t A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RD Write Cycle P0 BUS (D15-D8) D7-D0 WR(L), WRH demultiplexed bus, with/without read/write delay, extended ALE ST10R272L - ELECTRICAL CHARACTERISTICS 39u Address Figure 21 External memory cycle 41u 28h t 18 Data 20d ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS CLKOUT ALE A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RdCsx Write Cycle P0 BUS (D15-D8) D7-D0 WrCSx demultiplexed bus, with/without read/write delay, normal ALE, read/write chip select 64/ Address Data Out Figure 22 External memory cycle Data In t 53d t 68d ...
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... CLKOUT t 5 ALE t A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 RdCSx Write Cycle P0 BUS (D15-D8) D7-D0 WrCSx demultiplexed bus, no read/write delay, extended ALE, read/write chip select ST10R272L - ELECTRICAL CHARACTERISTICS Address Figure 23 External memory cycle Data 53d 46 t 68d Data Out ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS 16.3.5 CLKOUT and READY/READY 3 Parameter CLKOUT cycle time CLKOUT high time CLKOUT low time 1) CLKOUT rise time 1 CLKOUT fall time CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT ...
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... If the Asynchronous READY (or READY) signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). ST10R272L - ELECTRICAL CHARACTERISTICS READY Running cycle 1) waitstate ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS 6 Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7 The next external bus cycle may start here. ...
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... Parameter HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive ST10R272L - ELECTRICAL CHARACTERISTICS T = -40 to +85 ° Max. CPU Clock = 50 MHz Symbol min. max. t ...
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... HLDA 1) BREQ CSx (On P6.x) Other Signals Figure 25 External bus arbitration, releasing the bus 1 The ST10R272L will complete the running bus cycle before granting bus access. 2 This is the first opportunity for BREQ to become active. 3 The CS outputs will be resistive high (pullup) after t 70/ ...
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... This is the last chance for BREQ to trigger the regain-sequence indicated. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be de-activated without the ST10R272L requesting the bus. 2 The next ST10R272L driven bus cycle may start here. ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS 16.3.7 External Hardware Reset = 3 Parameter Symbol 1) t Sync. RSTIN low time 70 RSTIN low to internal t 71 reset sequence start internal reset sequence (RSTIN internally pulled low) RSTIN rising edge to inter nal reset condition end PORT0 system start-up ...
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... Other IOs t 77 Figure 27 External asynchronous hardware reset (power-up reset): Vpp low 1 The ST10R272L is reset in its default state asynchronously with RSTIN. The internal RAM content may be altered if an internal write access is in progress power-up, RSTIN must be asserted t 3 Internal pullup devices are active on the PORT0 lines input level is high if the respec- tive pin is left open - or is low if the respective pin is connected to an external pulldown device ...
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... Internal pullup devices are active on the PORT0 lines. Their input level is high if the respective pin is left open low if the respective pin is connected to an external pull- down device by resistive high (pullup) after t 5 The ST10R272L starts execution here at address 00’0000h. 6 RSTOUT stays active until execution of the EINIT (End of Initialization) instruction. 7 Activation of the IO pins is controlled by software ...
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... Write data hold after shift edge Write data hold after latch edge Read data active after latch edge Read data setup time before latch edge Read data hold time after latch edge Table 22 Synchronous serial port timing ST10R272L - ELECTRICAL CHARACTERISTICS = -40 to +85 °C A Max. Baudrate ...
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... ST10R272L - ELECTRICAL CHARACTERISTICS 1) SSPCLK t 205 SSPCEx t 207 SSPDAT 1) SSPCLK SSPCEx SSPDAT last Wr. Bit 1 The transition of shift and latch edge of SSPCLK is programmable. This figure uses the falling edge as shift edge (drawn bold). 2 The bit timing is repeated for all bits to be transmitted or received. ...
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... I C system is granted provided that the system conforms to the I Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain ST10R272L - PACKAGE MECHANICAL DATA Temperature range 0°C to 70°C -40°C to +85°C 2001 STMicroelectronics - All Rights Reserved. ...