IDT49C466 Integrated Device Technology, Inc., IDT49C466 Datasheet
IDT49C466
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IDT49C466 Summary of contents
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... Implementing a modified Hamming code, the IDT49C466/A corrects all single bit hard and soft errors, and detects all double bit errors. The read/ write FIFOs can store up to sixteen words. FIFO full and empty flags indicate whether additional data can be written to or read from the EDC ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT JECTIO MUX IN KBIT BYTE MUX MUX MUX 2 COMMERCIAL TEMPERATURE RANGE MUX MUX BFF W BEF W ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PIN CONFIGURATION 208 1 GND MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 SDOLE MOE MDILE MD31 GND ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PIN DESCRIPTION Pin Name I/O Data Buses SD I/O System Data Bus bidirectional 64-bit bus interfacing to the system or CPU. When System Output Enable, SOE, 0-63 is HIGH or Byte Enable I/O Memory Data Bus bidirectional 64-bit bus interfacing to the memory. During a read cycle, (MOE HIGH) memory data 0-63 is input for error detection and correction ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PIN DESCRIPTION (cont.) Pin Name I/O RBSEL I Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output latch). When LOW, the MD output latch is selected. RBEN I Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH transition of the memory clock ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT DETAILED DESCRIPTION — 64-BIT MODIFIED HAMMING CODE - CHECKBIT ENCODING CHART Generated Checkbits Parity CB0 Even (XOR) CB1 Even (XOR) CB2 Odd (XNOR) CB3 Odd (XNOR) CB4 Even (XOR) CB5 Even (XOR) CB6 ...
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... IDT49C466 OPERATION The EDC is involved in two types of operation — memory reads and memory writes. With the IDT49C466, both these can be accomplished by utilizing either of two possible data paths — one incorporating the FIFO and the other without the FIFO. These operations are treated separately below. ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MD LATCH OUT LATCH RITE BUFFER BE 0-7 Memory Read During a memory read, data and the corresponding input checkbits are read from the MD bus and CBI respectively. The memory and checkbit 0-7, data may both be latched as they come in (MD Latch In and MD Checkbit latch) by the MDILE signal ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT R/W FIFO Operation At Boundaries In the 49C466 the write pointer is incremented on every FIFO write. Similarly the read pointer is incremented on every FIFO read. In most cases on a FIFO read, the last data read remains at the output of the FIFO, until the read pointer is further incremented ...
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... SD and those that come from MD, as illustrated in Figure 1. EDC Modes The IDT49C466 has five modes of operation. Refer to the Operating Mode Description table for a description of the modes. The Error Data Output mode is useful for memory initialization as described below ...
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... Bit # "Error" condition Bit # "Multiple bit Error" condition Diagnostics The diagnostic ability of the IDT49C466 rests on a set of 6 registers that provide error logging information. These include the checkbit register, error count register, error type register, two syndrome registers and the error data register ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT ABSOLUTE MAXIMUM RATINGS Symbol Rating V Power Supply Voltage CC V Terminal Voltage with TERM Respect to Ground T Temperature Under Bias BIAS T Storage Temperature STG I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC PARAMETERS PROPAGATION DELAY TIMES Number Parameter From Input GENERATE (WRITE) PARAMETERS Without Write FIFO BEn BEn Pxin PPE 4 t SDin SDin SDin SPE With Write FIFO MCLK (Lo-Hi MCLK (Lo-Hi) MMD 9 t WBSEL ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT PROPAGATION DELAY TIMES FROM LATCH ENABLES Number Parameter From Input 21 t MDILE (Lo-Hi) MLE 22 t MDILE (Lo-Hi) MLME 23 t MDILE (Lo-Hi) MLP 24 t MDILE (Lo-Hi) MLS 25 t MDOLE (Hi-Lo) MOLS 26 t MDOLE (Hi-Lo) ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT BYTE MERGE TIMES Number Parameter From Input 36 t SCLK (Lo-Hi) SCM 37 t MDOLE (Hi-Lo) MDM 38 t RBSEL RBM NOTE: 1. (Lo-Hi) indicates LOW-to-HIGH transition and vice versa. ENABLE AND DISABLE TIMES (1) Number Parameter ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT SET-UP AND HOLD TIMES (1) Number Parameter From Input 52 t CBI Set-up CMLS 53 t CBI Hold CMLH 54 t MDIN Set-up MMLS 55 t MDIN Hold MMLH 56 t CBI Set-up (Correct) CMOLS 57 t CBI Hold (Correct) ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT MINIMUM PULSE WIDTH (1) Number Parameter From Input 85 t Min. RS1 LOW time Min. MDILE HIGH time MLE 87 t Min. MDOLE LOW time MDOLE 88 t Min. SDILE HIGH time SLE 89 t Min. S/MCLK HIGH time ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load SD0-15 SCLK MEN W BSEL SOE SCLK (W CLK) SD0-63 W BEN W BFF MCLK (RCLK) W BREN GND to 3V 1V/ns 1 ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT M CLK (RCLK) W BREN W BEF W BSEL SD OLE D0-63 CBSYN0-7 write SCLK (W CLK) Figure 6. WFIFO Read and Checkbit Generate Timing (Write Cycle) read t ENH CSD SKEW 2 19 COMMERCIAL TEMPERATURE RANGE Dout D1 t CECZx Valid Checkbits out ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT RBSEL 0- out CBI0 DILE write LK) t ENS RBEN RBFF t SKEW 1 SCLK (RCLK Checkbits ENH t FF read Figure 7. RFIFO Write Timing (Read Cycle) 20 COMMERCIAL TEMPERATURE RANGE ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT SCLK (R CLK) RBREN RBEF M CLK (W C LK) RBSEL SOE BE 0-7 SD 0-63 P 0-7 read t ENH t ENS write t SKEW 2 t SESZx t BESZx t SEPZx t BEPZx Figure 8. RFIFO Read Timing (Read Cycle) 21 COMMERCIAL TEMPERATURE RANGE t SSD SD out (corrected data) ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT CLK (SCLK / M CLK ATA (SD /MD) W CLK (SC LK/MC LK) t ENS BU FFER ENABLE (W BEN/ RBEN) t RSF FIFO RESET (RS1) BUFFER EMPTY FLAG (WBEF RSF t RSF Figure 9. FIFO (WFIFO/RFIFO) Reset Timing dataxx dumm y write Figure 10 ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT BE0-7 SOE SD0-63 SDILE SDOLE M D0- MDILE MDOLE RBSEL W BSEL NOTE not a propagation delay. For partial word write operations t MMOE SDin Dy t SSCS t SSCH external tristate M Din OEm OLS MMO LH Figure 11. Partial Word Write/Byte Merge Timing ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT BE0-7 SOE SD dum m y write SCLK MCLK t ENS W BEN W BREN W BSEL M D RBEN t ENS RBREN RBSE Figure 12. Partial Word Write/Byte Merge Timing using both RFIFO and WFIFO SESXZ Data SSCS SSCH read ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT invalid data SD 0-63 dum m y write SCLK (W CLK) t RSS RS1 BEF M CLK (RCLK) W BREN Figure 13. Write FIFO Write Timing with Clock Skew Violation M D0-63 CB0-7 MDILE SYNCLK SSCS SSCH ignored (no skew) M Din ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT TEST CIRCUITS FOR ALL OUTPUTS OUT V IN Pulse D.U.T. Generator R T SET-UP, HOLD, AND RELEASE TIMES DATA INPUT t SU TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR t SU CLOCK ENABLE ETC ...
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... IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT ORDERING INFORMATION IDT 49C466 X XX Device Type Speed Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 X Process/ Tem perature Range Blank Com m ercial (0 ° +70 ° C) PQF Plastic Quad Flatpack Blank Standard speed ...