IDT7008 Integrated Device Technology, Inc., IDT7008 Datasheet

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IDT7008

Manufacturer Part Number
IDT7008
Description
HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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IDT7008L15J
Manufacturer:
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Quantity:
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©2000 Integrated Device Technology, Inc.
NOTES:
1. BUSY is an input as a Slave (M/S = V
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 25/35/55ns (max.)
– Industrial: 55ns (max.)
– Commercial: 20/25/35/55ns (max.)
Low-power operation
– IDT7008S
– IDT7008L
Dual chip enables allow for depth expansion without
external logic
Active: 750mW (typ.)
Standby: 5mW (typ.)
Active: 750mW (typ.)
Standby: 1mW (typ.)
BUSY
I/O
SEM
INT
A
0-7L
A
15L
0L
L
L
L
(1,2)
(2)
R/W
CE
CE
OE
0L
1L
L
L
Decoder
Address
R/W
CE
CE
IL
OE
) and an output when it is a Master (M/S = V
1L
0L
L
L
16
HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
Control
I/O
ARBITRATION
SEMAPHORE
INTERRUPT
MEMORY
ARRAY
LOGIC
64Kx8
7008
M/S
1
(1)
IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
M/S = V
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
IH
).
Control
I/O
IH
IL
for BUSY input on Slave
for BUSY output flag on Master,
16
Address
Decoder
CE
OE
R/W
CE
0R
1R
R
R
R/W
CE
CE
OE
3198 drw 01
IDT7008S/L
0R
1R
R
R
I/O
BUSY
A
A
SEM
INT
15R
0R
0-7R
R
R
(2)
R
DSC 3198/6
(1,2)

Related parts for IDT7008

IDT7008 Summary of contents

Page 1

... BUSY and INT are non-tri-state totem-pole outputs (push-pull). ©2000 Integrated Device Technology, Inc. HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM IDT7008 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device for BUSY output flag on Master, M ...

Page 2

... Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7008 is packaged in a 84-pin Ceramic Pin Grid Array (PGA), a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad Flatpack (TQFP). ...

Page 3

... This text does not indicate orientation of the actual part marking. 2. All Vcc pins must be connected to power supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. All GND pins must be connected to ground supply. Military, Industrial and Commercial Temperature Ranges IDT7008PF (4) PN100-1 100-Pin TQFP (5) Top View 3 6 ...

Page 4

... This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part marking. Military, Industrial and Commercial Temperature Ranges 10R 12R 15R 11R 14R GND NC 5R 13R 2R 73 M/S R IDT7008G 74 (4) G84-3 GND 84-Pin PGA (5) 78 Top View Vcc 5L 13L 11L 14L ...

Page 5

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM < 0.2V >V -0. >V -0. <0.2V NOTES: 1. Chip Enable references are shown above with the actual CE (1) Inputs Outputs CE (2) OE SEM R/W I High DATA DATA High-Z NOTES – – 15L 0R 15R. 2. Refer to Chip Enable Truth Table. ...

Page 6

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Symbol Rating Commercial & Industrial (2) V Terminal Voltage -0.5 to +7.0 TERM with Respect to GND T Temperature -55 to +125 BIAS Under Bias Storage -65 to +150 T STG Temperature I DC Output Current 50 OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 7

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Symbol Parameter I Dynamic Operating CC Current (Both Ports Active) I Standby Current SB1 (Both Ports - TTL Level Inputs) I Standby Current SB2 (One Port - TTL Level Inputs) I Full Standby Current SB3 (Both Ports - All CMOS Level Inputs) ...

Page 8

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load ADDR ( R/W DATA OUT BUSY OUT ( NOTES: 1. Timing depends on which signal is asserted last CE. 2. Timing depends on which signal is de-asserted first CE or OE. ...

Page 9

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Symbol Parameter READ CYCLE t Read Cycle Time RC t Address Access Time AA (4) t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change OH (1,2) t Output Low-Z Time LZ (1,2) t Output High-Z Time ...

Page 10

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM ADDRESS OE (9,10 SEM ( R/W DATA (4) OUT DATA IN ADDRESS (9,10 SEM ( R/W DATA IN NOTES must be HIGH during all address transitions write occurs during the overlap ( measured from the earlier R/W (or SEM or R/W) going HIGH to the end of write cycle. ...

Page 11

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM VALID ADDRESS SEM DATA R/W OE NOTES for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table "DATA VALID" represents all I/O's (I/O - I/O OUT 0 A 0"A" (2) SIDE "A" ...

Page 12

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM Symbol Parameter BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable Low t BAC BUSY Access Time from Chip Enable High ...

Page 13

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM ADDR "A" "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins refer to Chip Enable Truth Table IL for the reading port. IL (SLAVE), then BUSY is an input (BUSY 4 ...

Page 14

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM BUSY ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" BUSY S ADDR "A" t APS ADDR "B" BUSY "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...

Page 15

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM ADDR "A" "A" R/W "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...

Page 16

... NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7008 are L R push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address is not met, either BUSY and enable inputs of this port ...

Page 17

... BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT7008 RAM the BUSY pin is an output if the part is used as a master (M/S pin = V the BUSY pin is an input if the part used as a slave (M/S pin = V in Figure 3 ...

Page 18

... The eight semaphore flags reside within the IDT7008 in a separate memory space from the Dual-Port RAM. This address space is accessed by placing a LOW input on the SEM pin (which acts as a chip select for the semaphore flags) and using the other control pins (Address, CE, and R/W) as they would be used in accessing a standard Static RAM ...

Page 19

... IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM IDT XXXXX A 999 Device Power Speed Type NOTE: 1. Industrial temperature range is available on selected TQFP packages in standard power. For other speeds, packages and powers contact your sales office. 1/6/99: Initiated datasheet document history Converted to new format ...

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