IDT70261 Integrated Device Technology, Inc., IDT70261 Datasheet
IDT70261
Available stocks
Related parts for IDT70261
IDT70261 Summary of contents
Page 1
... Integrated Device Technology, Inc. HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM WITH INTERRUPT IDT70261 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M for BUSY output flag on Master, M for BUSY input on Slave ...
Page 2
... High-Speed 16K x 16 Dual-Port Static RAM with Interrupt The IDT70261 is a high-speed 16K x 16 Dual-Port Static RAM. The IDT70261 is designed to be used as a stand-alone Dual-Port RAM combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32- bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic ...
Page 3
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Ambient Grade Temperature Commercial + Industrial - + NOTES: 1. This is the parameter (1) Inputs NOTE — — 13L 0R 13R. Inputs NOTE: 1. There are eight semaphore flags written to via I/O Symbol GND Vcc 5.0V 10% GND + 0V 5.0V 10% ...
Page 4
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol Rating (2) V Terminal Voltage TERM with Respect to GND T Temperature BIAS Under Bias T Storage STG Temperature I DC Output OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
Page 5
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol Parameter CE I Dynamic Operating Current CC SEM (Both Ports Active Standby Current SB1 SEM (Both Ports - TTL Level Inputs Standby Current SB2 (One Port - TTL Level Inputs) Active Port Outputs Open, f=f ...
Page 6
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ACE (3) t Byte Enable Access Time ABE t Output Enable Access Time AOE t Output Hold from Address Change ...
Page 7
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt ADDR DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE, CE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY 3 ...
Page 8
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol Parameter WRITE CYCLE t Write Cycle Time WC (3) t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW (3) t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) ...
Page 9
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt ADDRESS OE (9) CE SEM (4) DATA OUT DATA IN ADDRESS CE SEM ( DATA IN NOTES and during all address transitions write occurs during the overlap ( measured from the earlier R/W (or SEM or R/W) going During this period, the I/O pins are in the output state and input signals must not be applied. ...
Page 10
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt VALID ADDRESS SEM I R/W OE NOTES and for the duration of the above timing (both write and read cycle "DATA VALID" represents all I/O's (I/O -I/O OUT 0 A 0"A" (2) SIDE "A" A 0"B" (2) SIDE "B" ...
Page 11
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt Symbol BUSY S TIMING ( BUSY t Access Time from Address Match BAA BUSY t Disable Time from Address Not Matched BDA BUSY t Acce ss Time from Chip Enable Low BAC BUSY t Acce ss Time from Chip Enable High ...
Page 12
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt ADDR "A" "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES ensure that the earlier of the two ports wins IL for the reading port. IL (slave), BUSY is an input. Then for this example BUSY 4 ...
Page 13
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt BUSY ADDR "A" and "B" +- "A" (2) t APS +- "B" *75; "B" BUSY ADDR "A" t APS ADDR "B" BUSY "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...
Page 14
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt ADDR "A" ( "A" "A" INT "B" ADDR "B" ( "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”. ...
Page 15
... NOTES: 1. Pins BUSY and BUSY are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70261 are L R push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes. 2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address is not met, either BUSY and enable inputs of this port ...
Page 16
... BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT70261 RAM the BUSY pin is an output if the part is used as a master (M/S pin = V pin is an input if the part used as a slave (M/S pin = V Figure 3 ...
Page 17
... Perhaps the simplest application of semaphores is their application as resource markers for the IDT70261’s Dual-Port RAM. Say the 16K x 16 RAM was to be divided into two blocks which were to be dedicated at any one time to servicing either the left or right port. Semaphore 0 could ...
Page 18
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt of the resource after the left processor, it would read back a one in response to the zero it had attempted to write into Semaphore 0. At this point, the software could choose to try and gain control of the second 8K section by writing, then reading a zero into Semaphore 1 ...
Page 19
... IDT70261S/L High-Speed 16K x 16 Dual-Port Static RAM with Interrupt IDT XXXXX A 999 Device Power Speed Type 1/14/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Pages 2 Added additional notes to pin configurations 6/4/99: Changed drawing format Page 1 Corrected DSC number ...