IDT71421 Integrated Device Technology, Inc., IDT71421 Datasheet
IDT71421
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IDT71421 Summary of contents
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... MASTER IDT71321 easily expands data bus width to 16-or- more-bits using SLAVE IDT71421 On-chip port arbitration logic (IDT71321 only) BUSY output flag on IDT71321; BUSY input on IDT71421 Fully asynchronous operation from either port Battery backup operation – 2V data retention (LA only) TTL-compatible, single 5V ±10% power supply Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP Industrial temperature range (– ...
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... RAMs with internal interrupt logic for interprocessor communications. The IDT71321 is designed to be used as a stand-alone 8-bit Dual- Port Static RAM "MASTER" Dual-Port Static RAM together with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap- proach in 16-or-more-bit memory system applications results in full speed, error-free operation without the need for additional discrete logic ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Symbol Parameter Conditions C Input Capacitance IN C Output Capacitance V OUT NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from from 3V to 0V. ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Symbol Parameter I Dynam ic Op erating CE and Current Outputs Ope n (2) ( rts Active ) MAX CE and CE I Stand by Curre nt SB1 L (2) ( rts - TTL MAX Level Inp uts Stand by Curre SB2 "A" IL (One TTL ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Symbol Parameter ( Input Leakage Current LI ( Output Leakage Current LO V Output Low Voltage (I/O -I Open Drain Output V OL Low Voltage (BUSY/INT) V Output High Voltage OH NOTE Vcc < 2.0V leakages are undefined. Symbol Parameter ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT 775 Figure 1. AC Output Test Load BUSY or INT Figure 3. BUSY and INT AC Output Test Load GND to 3 ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time AOE t Output Hold from Address Change OH (1,3) t Output Low-Z Time LZ (1,3) ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts ADDRESS DATA PREVIOUS DATA VALID OUT BUSY OUT NOTES and Address is valid prior to the coincidental with CE transition LOW delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BDD BUSY has no relationship to valid output data ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Symbol WRITE CYCLE (2) t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW t Address Set-up Time AS (3) t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts ADDRESS R/W DATA (4) OUT DATA IN ADDRESS CE ( R/W DATA IN NOTES must be HIGH during all address transitions write occurs during the overlap ( measured from the earlier R/W going HIGH to the end of the write cycle. ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Symbol BUSY TIMING (For MASTER 71321) BUSY Access Time from Address t BAA BUSY Disable Time from Address t BDA BUSY Access Time from Chip Enable t BAC BUSY Disable Time from Chip Enable ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT"B" NOTES ensure that the earlier of the two ports wins for the reading port All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A". ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts BUSY ADDR "A" AND "B" CE "B" (2) t APS CE "A" BUSY "A" BUSY ADDR ADDRESSES MATCH "A" (2) t APS ADDR "B" BUSY "B" NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts Symbol INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTES: 1. 'X' in part numbers indicates power rating (SA or LA). 2. Industrial temperature: for other speeds, packages and powers contact your sales office. ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts (1) Left or Right Port CE OE R DATA DATA NOTES – – 10R 0L 10L 2. If BUSY = L, data is not written BUSY = L, data may not be valid, see t WDD 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE ...
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... BUSY indication, and to output that indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs the BUSY pin is an output if the part is Master (IDT7132), and the BUSY pin is an input if the part is a Slave (IDT7142) as shown in Figure 3 ...
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... IDT71321SA/LA and IDT71421SA/LA High Speed Dual-Port Static RAM with Interrupts IDT XXXX A 999 Device Type Power Speed NOTE: 1. Industrial temperature range is available in selected PLCC packages in standard power. For other speeds, packages and powers contact your sales office. 3/24/99: Initiated datasheet document history ...