IDT71V30 Integrated Device Technology, Inc., IDT71V30 Datasheet
IDT71V30
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IDT71V30 Summary of contents
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... OE L R/W L (2) INT L NOTES: 1. IDT71V30: BUSY outputs are non-tristatable push-pulls. 2. INT outputs are non-tristable push-pull output structure. ©2000 Integrated Device Technology, Inc. HIGH-SPEED 3. DUAL-PORT STATIC RAM On-chip port arbitration logic Interrupt flags for port-to-port communication Fully asynchronous operation from either port Battery backup operation, 2V data retention (L Only) TTL-compatible, single 3.3V ± ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts The IDT71V30 is a high-speed Dual-Port Static RAM. The IDT71V30 is designed to be used as a stand-alone 8-bit Dual-Port SRAM. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Symbol Rating (2) V Terminal Voltage TERM with Respect to GND T Temperature BIAS Under Bias T Storage STG Temperature DC Output I OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Symbol Parameter I Dynamic Operating Current (Both Ports Active) Outputs Disabled Standby Current CE SB1 L (Both Ports - TTL Level Inputs) I Standby Current CE SB2 "A" (One Port - TTL Level Active Port Outputs Disabled, Inputs) f=f MAX I Full Standby Current (Both ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT BUSY 435 INT Figure 1. AC Output Test Load Symbol READ CYCLE t Read Cycle Time RC t Address Access Time ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts ADDRESS t OH DATA OUT PREVIOUS DATA VALID BUSY OUT NOTES and Address is valid prior to the coincidental with CE transition LOW delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultaneous read operations BUSY has 2 ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Symbol Parameter WRITE CYCLE t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) t Output High-Z Time ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts ADDRESS R/W DATA (4) OUT DATA IN ADDRESS CE ( R/W DATA IN NOTES must be HIGH during all address transitions write occurs during the overlap ( measured from the earlier R/W going HIGH to the end of the write cycle. ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address Not Matched t BDA BUSY Access Time from Chip Enable t BAC BUSY Disable Time from Chip Enable t BDC Write Hold After BUSY ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts R/W BUSY R/W NOTES: must be met for BUSY BUSY is asserted on port 'B' blocking R/W , until BUSY 'B' 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts Symbol Parameter INTERRUPT TIMING t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTES: 1. 'X' in part number indicates power rating (S or L). 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. ...
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... MATCH (2) NOTES: 1. Pins BUSY and BUSY are both outputs for IDT71V30. BUSY L R IDT71V30 are non-tristatable push-pull. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'H' if the inputs to the opposite port became stable after the address and is not met, either BUSY enable inputs of this port ...
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... The IDT71V30 provides two ports with separate control, address and I/O pins that permit independent access for reads or writes to any location in memory. The IDT71V30 has an automatic power down feature controlled by CE. The CE controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ...
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... IDT71V30S/L High-Speed Dual-Port Static RAM with Interrupts IDT XXXX A 999 Device Type Power Speed Package NOTE: 1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office. 12/9/98: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections ...