IDT71V432 Integrated Device Technology, Inc., IDT71V432 Datasheet

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IDT71V432

Manufacturer Part Number
IDT71V432
Description
32K x 32 CacheRAM 3.3V Synchronous SRAM Burst Counter Single Cycle Deselect
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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CacheRAM is a trademark of Integrated Device Technology.
Pentium processor is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
©2000 Integrated Device Technology, Inc.
organized as 32K x 32 with full support of the Pentium™ and PowerPC™
CS
CLK
I/O
A
CE
OE
GW
BWE
BW
ADV
ADSC
ADSP
LBO
ZZ
V
V
0
DD
SS
32K x 32 memory configuration
Supports high-performance system speed:
Commercial and Industrial:
— 5ns Clock-to-Data Access (100MHz)
— 6ns Clock-to-Data Access (83MHz)
— 7ns Clock-to-Data Access (66MHz)
Single-cycle deselect functionality (Compatible with
Micron Part # MT58LC32K32D7LG-XX)
LBO input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Operates with a single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
The IDT71V432 is a 3.3V high-speed 1,048,576-bit CacheRAM
–A
0
0
1,
–I/O
, CS
14
BW
31
1
2,
BW
3,
BW
4
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Linear / Interleaved Burst Order
Sleep Mode
Data Input/Output
Ground
Address Inputs
Address Status (Cache Controller)
Address Status (Processor)
3.3V Power
32K x 32 CacheRAM™
3.3V Synchronous SRAM
Burst Counter
Single Cycle Deselect
1
processor interfaces. The pipelined burst architecture provides cost-
effective 3-1-1-1 secondary cache performance for processors up to
100 MHz.
control registers. Internal logic allows the CacheRAM to generate a self-
timed write based upon a decision which can be left until the extreme end
of the write cycle.
system designer, as the IDT71V432 can provide four cycles of data for
a single address presented to the CacheRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses will be defined by the internal burst counter
and the LBO input pin.
volume 3.3V CMOS process, and is packaged in a JEDEC Standard
14mm x 20mm 100-pin thin plastic quad flatpack (TQFP) for optimum board
density in both desktop and notebook applications.
The IDT71V432 CacheRAM contains write, data, address, and
The burst mode feature offers the highest level of performance to the
The IDT71V432 CacheRAM utilizes IDT's high-performance, high-
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Ground
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
DC
DC
Asynchronous
Asynchronous
IDT71V432
DSC-3104/05
3104 tbl 01

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IDT71V432 Summary of contents

Page 1

... The burst mode feature offers the highest level of performance to the system designer, as the IDT71V432 can provide four cycles of data for a single address presented to the CacheRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence ...

Page 2

... Synchronous chip enable used with CS I LOW IDT71V432. CE also gates ADSP. I N/A This is the clock input to the IDT71V432. All timing references for the device are made with respect to this input. I HIGH Synchronous active HIGH chip select. CS the chip. Synchronous active LOW chip select. CS ...

Page 3

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect LBO ADV CLK ADSC ADSP A – BWE Powerdown OE I/O –I Commercial and Industrial Temperature Ranges Burst CE Sequence 2 Burst Binary Logic Counter CLR CLK ADDRESS REGISTER 15 Byte 1 Write Register ...

Page 4

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Symbol Rating (2) Terminal Voltage with V TERM Respect to GND (3) V Terminal Voltage with TERM Respect to GND T Operating Temperature A T Temperature Under Bias BIAS T Storage Temperature STG P Power Dissipation Output Current ...

Page 5

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect 100 I DD I NOTES: 1. Pin 14 can either be directly connected Pin 64 can be left unconnected and the device will always remain in active mode. ...

Page 6

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Address Operation Used Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None Deselected Cycle, Power Down None ...

Page 7

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect GW Operation Read H Read H Write all Bytes L Write all Bytes H (2) Write Byte 1 H (2) Write Byte 2 H (2) Write Byte 3 H (2) Write Byte 4 H NOTES Don’t Care Multiple bytes may be selected during the same cycle. ...

Page 8

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Symbol Parameter |I | Input Leakage Current LI ZZ and LBO Input Leakage Current | Output Leakage Current Output Low Voltage (I/O –I Output High Voltage (I/O –I NOTE: 1. The LBO pin will be internally pulled to V ...

Page 9

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Symbol Parameter CLOCK PARAMETERS t Clock Cycle Time CYC (1) t Clock High Pulse Width CH (1) t Clock Low Pulse Width CL OUTPUT PARAMETERS t Clock High to Valid Data CD t Clock High to Data Change ...

Page 10

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 10 ...

Page 11

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 11 ...

Page 12

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges GW 6. ...

Page 13

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 13 ...

Page 14

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 14 ...

Page 15

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect CLK ADSP or ADSC ADDRESS Av DATA OUT NOTES: 1. ZZ, CE and OE are LOW for this cycle ADV, GW, BWE, BWx, and CS are HIGH for this cycle (Ax) represents the data for address Ax, etc. ...

Page 16

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges 6.42 16 ...

Page 17

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect IDT 71V432 S X Device Power Speed Type PART NUMBER SPEED IN MEGAHERTZ 71V432S5PF 71V432S6PF 71V432S7PF X PF Process/ Package Temperature Range Blank PARAMETER CD 100 MHz MHz MHz 7 ns 6.42 17 Commercial and Industrial Temperature Ranges Commercial ( +70 C) Industrial (– ...

Page 18

... IDT71V432, 32K x 32 CacheRAM 3.3V Synchronous SRAM with Burst Counter, Single Cycle Deselect 9/10/99 Pg. 3–5 Pg. 5 Pg. 11–14 Pg. 17 03/09/00 Pg 04/04/00 Pg. 16 08/09/00 08/17/01 CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc. ...

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