IDT71V65803 Integrated Device Technology, Inc., IDT71V65803 Datasheet

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IDT71V65803

Manufacturer Part Number
IDT71V65803
Description
256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
©2002 Integrated Device Technology, Inc.
(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT
R/W
CLK
I/O
A
CE
OE
CEN
BW
ADV/LD
LBO
ZZ
V
V
0
DD
SS
-A
0
256K x 36, 512K x 18 memory configurations
Supports high performance system speed - 150MHz
ZBT
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (V
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array(fBGA).
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit
1
1
-I/O
(3.8ns Clock-to-Data Access)
, V
, CE
, BW
18
DDQ
31
TM
2
, I/O
, CE
2
, BW
Feature - No dead cycles between write and read cycles
P1
2
3
-I/O
, BW
P4
4
DDQ
)
1
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Address Inputs
Advance burst address / Load new address
- BW
4
) control (May tie active)
TM
, or Zero Bus Turnaround.
256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
3.3V I/O, Burst Counter
Pipelined Outputs
1
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and
165 fine pitch ball grid array (fBGA) .
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
be suspended as long as necessary. All synchronous inputs are ignored when
(CEN) is high and the internal device registers will hold their previous values.
to deselect the device when desired. If any one of these three are not asserted
when ADV/LD is low, no new memory operation can be initiated. However,
any pending data transfers (reads or writes) will be completed. The data bus
will tri-state two cycles after chip is deselected or a write is initiated.
mode, the IDT71V65603/5803 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
cycle, and two cycles later the associated data cycle occurs, be it read or write.
The IDT71V65603/5803 contain data I/O, address and control signal
A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803 to
There are three chip enable pins (CE1, CE2, CE2) that allow the user
The IDT71V65603/5803 have an on-chip burst counter. In the burst
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance
Address and control signals are applied to the SRAM during one clock
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
IDT71V65603
IDT71V65803
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Static
Static
Static
N/A
DSC-5304/05
5304 tbl 01

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IDT71V65803 Summary of contents

Page 1

... CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100- pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and Zero Bus Turnaround. 165 fine pitch ball grid array (fBGA IDT71V65603 IDT71V65803 Input Synchronous Input Synchronous Input Asynchronous ...

Page 2

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Symbol Pin Function I Address Inputs ADV/LD Advance / Load I R/W Read / Write I CEN Clock Enable I BW Individual Byte I - Write Enables Chip Enables Chip Enable ...

Page 3

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs LBO Address A [0:17] CE1, CE2, CE2 R/W CEN ADV/LD BWx Clock Control Logic Clk 6.42 3 Commercial and Industrial Temperature Ranges 256Kx36 BIT ...

Page 4

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs LBO Address A [0:18] CE1, CE2, CE2 R/W CEN ADV/LD BWx Clock OE Symbol Parameter Min. V Core Supply Voltage 3.135 DD V I/O Supply Voltage 3 ...

Page 5

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Grade Temperature ( Commercial 0° +70° Industrial -40°C to +85°C 0V NOTES the "instant on" case temperature. A 100 I I DDQ DDQ ...

Page 6

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs 100 DDQ I I DDQ DDQ DDQ NOTES: 1. Pins 14, 16 and 66 do not have to be connected directly to V the input voltage is V ...

Page 7

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs DDQ I I DDQ DDQ DDQ DDQ DDQ I DDQ I DDQ I DDQ DDQ NOTES: 1. J3, J5, and R5 do not have to be directly connected ...

Page 8

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs ( I DDQ D I/O I DDQ E I/O I DDQ F I/O I DDQ G I/O I DDQ ( I/O I DDQ K I/O I DDQ L I/O I DDQ M I/O I DDQ N I DDQ ( LBO ( ( DDQ ...

Page 9

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs CEN (5) R/W Chip ADV/LD Enable L L Select Select Deselect NOTES Don’t Care When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle ...

Page 10

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs First Address Second Address Third Address (1) Fourth Address NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. ...

Page 11

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Cycle Address R/W ADV NOTES defined and High Low Don’t Care High Impedance. ...

Page 12

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Cycle Address R/W ADV NOTES High Low Don’t Care High Impedance defined and Cycle Address R/W ADV/LD ...

Page 13

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Cycle Address R/W ADV NOTES High Low Don’t Care High Impedance defined and Cycle Address R/W ADV/ n+1 ...

Page 14

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Cycle Address R/W ADV NOTES High Low Don’t Care Don’t Know High Impedance defined and Device Outputs are ensured High-Z after the first rising edge of clock upon power-up. ...

Page 15

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Symbol Parameter |I | Input Leakage Current LI LBO Input Leakage Current ( Output Leakage Current LO VO Output Low Voltage L V Output High Voltage OH NOTE: 1. The LBO pin will be internally pulled to V ...

Page 16

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Symbol Parameter t Clock Cycle Time CYC (1) Clock Frequency t F (2) Clock High Pulse Width t CH (2) Clock Low Pulse Width t CL Output Parameters t Clock High to Valid Data ...

Page 17

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 18

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 19

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6. ...

Page 20

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs CEN Commercial and Industrial Temperature Ranges 6.42 20 ...

Page 21

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs CS Commercial and Industrial Temperature Ranges 6. ...

Page 22

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6.42 22 ...

Page 23

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6.42 23 ...

Page 24

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 6.42 24 ...

Page 25

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs OE OE DATA OUT NOTE read operation is assumed progress. IDT XXXX S XX Device Power Speed Type CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc ...

Page 26

... IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs 12/31/99 Created new datasheet from obsolete devices IDT71V656 and IDT71V658 03/04/00 Pg. 1,14,15 Removed 166MHz speed grade offering; Added 150MHz speed grade offering 04/20/00 Pg ...

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