IDT723622 Integrated Device Technology, Inc., IDT723622 Datasheet
IDT723622
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IDT723622 Summary of contents
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... Low-power 0.8-Micron Advanced CMOS technology • Industrial temperature range (-40 able, tested to military electrical specifications DESCRIPTION: The IDT723622/723632/723642 is a monolithic, high-speed, low-power, CMOS Bidirectional SyncFIFO (clocked) memory which supports clock frequencies up to 67MHz and have read access times as fast as 11ns. Two independent 256/512/ 1024x36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions ...
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... AEA AEB and Almost-Empty ( , synchronized to the port clock that reads data from its array. Offset values for the Almost-Full and Almost-Empty flags of both FIFOs can be programmed from Port A. The IDT723622/723632/723642 is characterized for op- eration from PQ132-1 PQF Package TOP VIEW 5.22 AFA ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 PIN CONFIGURATION GND GND GND COMMERCIAL TEMPERATURE RANGE PN120-1 TQFP TOP VIEW 5. GND GND GND GND 61 3022 drw 03 3 ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port-A Data I/0 AEA Port-A Almost O -Empty Flag (Port A) AEB Port-B Almost O -Empty Flag (Port B) AFA Port-A Almost O -Full Flag (Port A) AFB Port-B Almost O -Full Flag (Port B35 Port-B Data ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 PIN DESCRIPTIONS (CONT.) Symbol Name I/O MBB Port-B Mailbox I Select MBF1 Mail1 Register O Flag MBF2 Mail2 Register O Flag ORA Output-Ready O Flag (Port A) ORB Output-Ready O Flag (Port B) RST1 FIFO1 Reset I RST2 FIFO2 Reset Port-A Write/ I Read Select ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UN- LESS OTHERWISE NOTED) Symbol V Supply Voltage Range CC (2) V Input Voltage Range I V (2) Output Voltage Range O I Input Clamp Current ( Output Clamp Current ( Continuous Output Current (V OUT I Continuous Current Through V ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERA- TURE RANGE (UNLESS OTHERWISE NOTED) Parameter Test Conditions 4. 5.5 V, One Input at 3 Other Inputs GND MHz MHZ OUT O NOTES: 1. All typical values are 5V This is the supply current when each input is at least one of the specified TTL voltage levels rather than ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPER- ATING FREE-AIR TEMPERATURE Symbol Parameter f Clock Frequency, CLKA or CLKB S t Clock Cycle Time, CLKA or CLKB CLK t Pulse Duration, CLKA or CLKB HIGH CLKH t Pulse Duration, CLKA and CLKB LOW ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C Symbol Parameter t Access Time, CLKA to A0-A35 and CLKB A to B0-B35 t Propagation Delay Time, CLKA to IRA and PIR CLKB to IRB t Propagation Delay Time, CLKA to ORA and ...
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... Valid programming values for the registers ranges from 1 to 252 for the IDT723622 508 for the IDT723632; and 1 to 1020 for the IDT723642. After all the offset registers are programmed from port A, the port-B input- ready flag (IRB) is set HIGH, and both FIFOs begin normal operation ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 port-B operation. The port-B control signals are identical to those of port A with the exception that the port-B write/read select ( the inverse of the port-A write/read select (W/ of the port-B data (B0-B35) outputs is controlled by the port- CSB B chip select ( ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 OUTPUT-READY FLAGS (ORA, ORB) The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the output-ready flag is HIGH, new data is present in the FIFO output register. When the output-ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored ...
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... IDT723622, IDT723632, or IDT723642 re- spectively. An almost-full flag is HIGH when the number of words in its FIFO is less than or equal to [256-(Y+1)], [512- (Y+1)], or [1024-(Y+1)] for the IDT723622, IDT723632, or IDT723642 respectively. Note that a data word present in the or greater FIFO output register has been read from memory. ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKA CLKB t RSTS RST1 FS1,FS0 IRA ORB t RSF AEB t RSF AFA t RSF MBF1 Figure 1. FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight NOTE: 1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value. CLKA 4 t FSS ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLK t t CLKH CLKL CLKA IRA t ENS CSA t ENS ENS MBA t ENS ENA A35 NOTE: 1. Written to FIFO1. t CLK t t CLKH CLKL CLKB IRB CSB W /RB MBB ENB B0 - B35 NOTE: 1. Written to FIFO2. t ENH t ENH t ENH t ENH ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLK t t CLKH CLKL CLKB ORB CSB W /RB MBB ENB t MDV B35 NOTE: 1. Read From FIFO1. t CLK t t CLKH CLKL CLKA ORA CSA MBA ENA t DMV A35 NOTE: 1. Read From FIFO2. t ENS t ENH t ENS t A (1) ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKA CSA LOW HIGH t t ENS ENH MBA t t ENS ENH ENA HIGH IRA A0 - A35 W1 t SKEW1 CLKB ORB Old Data in FIFO1 Output Register CSB LOW W HIGH /RB MBB LOW ENB B0 -B35 Old Data in FIFO1 Output Register NOTE: 1 ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKB CSB LOW W LOW / ENS MBB t ENS ENB HIGH IRB B35 W1 t SKEW1 CLKA Old Data in FIFO2 Output Register ORA CSA LOW R LOW W/ A MBA LOW ENA A0 -A35 Old Data in FIFO2 Output Register NOTE the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output SKEW1 register in three CLKA cycles ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLK t t CLKH CLKL CLKB CSB LOW W HIGH /RB MBB LOW t ENS ENB HIGH ORB B0 -B35 Previous Word in FIFO1 Output Register CLKA IRA FIFO1 Full CSA LOW R HIGH W A MBA ENA A0 - A35 NOTE the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLK t t CLKH CLKL CLKA CSA LOW LOW MBA LOW t ENS ENA HIGH ORA A0 -A35 Previous Word in FIFO2 Output Register CLKB IRB FIFO2 FULL CSB LOW W LOW RB MBB ENB B0 - B35 NOTE the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKB t t ENH ENS ENB t SKEW2 CLKA AEA X2 Words in FIFO2 ENA NOTES the minimum time between a rising CLKB edge and a rising CLKA edge for SKEW2 the rising CLKB edge and rising CLKA edge is less than t ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKB t ENS ENB AFB [D-(Y2+1)] Words in FIFO2 CLKA ENA NOTES the minimum time between a rising CLKB edge and a rising CLKA edge for SKEW2 the rising CLKB edge and rising CLKA edge is less than t CSB W 2. FIFO2 write ( ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKB CSB W /RB MBB ENB B0 - B35 CLKA MBF2 CSA MBA ENA A35 FIFO2 Output Register t ENH t ENS PMF t MDV t PMR W1 (Remains valid in Mail 2 Register after read) Figure 16. Timing for Mail2 Register and 5.22 COMMERCIAL TEMPERATURE RANGE ...
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... Once the capacitance load per data-output channel and the number of IDT723622/723632/723642 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. With I taken from Figure 17, the maximum power dissipation (PT) of the IDT723622/723632/723642 may be CC(f) calculated by: ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 PARAMETER MEASUREMENT INFORMATION From Output Under Test Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PZL t PLZ Low-Level Output t PZH High-Level Output t PHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTE: 1 ...
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... IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 ORDERING INFORMATION IDT XXXXXX X XX Device Type Power Speed X X Package Process/ Temperature Range BLANK Commercial ( + Thin Quad Flat Pack PQF Plastic Quad Flat Pack 15 Commercial Only 20 Clock Cycle Time (t 30 Speed in Nanoseconds L Low Power ...