IDT723623 Integrated Device Technology, Inc., IDT723623 Datasheet

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... Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Industrial temperature range (– + available The IDT723623/723633/723643 are monolithic, high-speed, low-power, CMOS unidirectional Synchronous (clocked) FIFO memories which support clock frequencies MHz and have read access times as fast as 8 ns. ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 The 256/512/1,024 x 36 dual-port SRAM FIFO buffers data from port A to port B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice of Big- or Little-Endian configurations. These devices are synchronous (clocked) FIFOs, meaning each port employs a synchronous interface ...

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... Initiating any operation (by activating control CC inputs) will immediately take the device out of the Power Down state. The IDT723623/723633/723643 are characterized for operation from Industrial temperature range (- + available by special order. They are fabricated using IDT’s high speed, submicron CMOS technology. ...

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... FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 16 for the IDT723623, 18 for the IDT723633, and 20 for the IDT723643. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 Symbol Name I/O MBF2 MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 Mail2 Register O register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port Flag A read is selected and MBA is HIGH ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 Symbol V Supply Voltage Range Input Voltage Range ( I V (2) Output Voltage Range O I Input Clamp Current (V < Output Clamp Current (V = < Continuous Output Current (V OUT O I Continuous Current Through Storage Temperature Range ...

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... All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected S to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of IDT723623/723633/723643 inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 (Commercial 5.0V ± Symbol Parameter f Clock Frequency, CLKA or CLKB S t Clock Cycle Time, CLKA or CLKB CLK t Pulse Duration, CLKA or CLKB HIGH CLKH t Pulse Duration, CLKA and CLKB LOW CLKL t Setup Time, A0-A35 before CLKA and B0-B35 before CLKB DS Setup Time, CSA and W/RA before CLKA ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 (Commercial 5.0V ± Symbol t Access Time, CLKA to A0-A35 and CLKB to B0-B35 A Propagation Delay Time, CLKA to FF/IR t WFF Propagation Delay Time, CLKB to EF/OR t REF Propagation Delay Time, CLKB PAE Propagation Delay Time, CLKA to AF ...

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... Figure 3 (Reset) for a First Word Fall Through select timing diagram. PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS Two registers in the IDT723623/723633/723643 are used to hold the offset values for the Almost-Empty and Almost-Full flags. The Almost-Empty flag (AE) Offset register is labeled X and Almost-Full flag (AF) Offset register is labeled Y. The offset registers can be loaded with preset values during the reset of the FIFO, programmed in parallel using the FIFO’ ...

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... 252 for the IDT723623 508 for the IDT723633; and 1 to 1,020 for the IDT723643. After all the offset registers are programmed from Port A the FIFO begins normal operation. — SERIAL LOAD To program the X and Y registers serially, initiate a Reset with SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH transition of RS1 ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 can be programmed from 1 to 508 (IDT723623 1,020 (IDT723633 2,044 (IDT723643). When the option to program the offset registers serially is chosen, the Full/ Input Ready (FF/IR) flag remains LOW until all register bits are written. FF/IR is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO operation ...

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... Almost-Empty flag and Almost-Full flag offset programming section). An Almost- Full flag is LOW when the number of words in its FIFO is greater than or equal to (256-Y), (512-Y), or (1,024-Y) for the IDT723623, IDT723633, or IDT723643 respectively. An Almost-Full flag is HIGH when the number of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723623, IDT723633, or IDT723643 respectively ...

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... Full/Input Ready flag is set HIGH, as shown in Figure 2. Only 36-bit long word data is written to or read from the FIFO memory on the IDT723623/723633/723643. Bus-matching operations are done after data is read from the FIFO RAM. These bus-matching operations are not available when transferring data via mailbox registers. Furthermore, both the word- and byte-size bus selections limit the width of the data bus that can be used for mail register operations ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 BYTE ORDER ON PORT SIZE BYTE ORDER ON PORT SIZE SIZE SIZE SIZE A35 A27 A26 A18 A17 B35 B27 B26 B18 B17 (a) LONG WORD SIZE B35 B27 B26 B18 B17 B9 A B35 B27 ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA CLKB t RSTS (3) RS1/RS2 BE/FWFT SPM FS1,FS0 FF/IR EF/OR t RSF AE t RSF AF t RSF MBF1, MBF2 NOTES: 1. PRS must be HIGH during Reset BE/FWFT is HIGH, then EF/OR will go LOW one CLKB cycle earlier than in this case where BE/FWFT is LOW. ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA 1 4 RS1 t FSS t FSH SPM t FSS t FSH 0,0 FS1,FS0 FF/IR ENA A0-A35 NOTE: 1. CSA = LOW, W/RA = HIGH, MBA = LOW not necessary to program offset register on consecutive clock cycles. Figure 5. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset. (IDT Standard and FWFT Modes) ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 CLK t CLKH t CLKL CLKA FF/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ENA t DS A0-A35 NOTE: 1. Written to FIFO. Figure 7. Port A Write Cycle Timing for FIFO (IDT Standard and FWFT Modes) t CLK ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKB FF/OR HIGH CSB W/RB MBB ENB B0-B17 (Standard Mode) OR B0-B17 (FWFT Mode) NOTE: 1. Unused word B18-B35 are indeterminate. DATA SIZE TABLE FOR WORD READS (1) SIZE MODE BM SIZE NOTE selected at Reset: BM and SIZE must be static throughout device operation. ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKB EF/OR HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode MDV t B0-B8 EN (FWFT Mode) NOTE: 1. Unused bytes B9-B17, B18-B26, and B27-B35 are indeterminate. DATA SIZE TABLE FOR BYTE READS ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA LOW CSA W/RA HIGH t t ENS2 ENH MBA t t ENS2 ENH ENA IR HIGH A0-A35 W1 t SKEW1 CLKB FIFO Empty OR CSB LOW W/RB HIGH LOW MBB ENB B0-B35 Old Data in FIFO Output Register NOTES: 1 ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKA CSA LOW W/RA HIGH t ENS2 t MBA t ENS2 t ENA FF HIGH A0-A35 W1 t SKEW1 CLKB EF FIFO Empty CSB LOW W/RB HIGH LOW MBB ENB B0-B35 NOTES: is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge 1 ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB OR HIGH B0-B35 Previous Word in FIFO Output Register CLKA FIFO Full IR CSA LOW HIGH W/RA MBA ENA A0-A35 NOTES the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB EF HIGH B0-B35 Previous Word in FIFO Output Register CLKA FF FIFO Full CSA LOW W/RA HIGH MBA ENA A0-A35 NOTES: is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge 1 ...

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... FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO Maximum FIFO Depth = 256 for the IDT723623, 512 for the IDT723633, 1,024 for the IDT723643. ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 CLKB t ENS1 CSB t ENS1 W/RB t ENS2 MBB t ENS2 ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA t EN FIFO Output Register A0-A35 NOTE Port B is configured for word size, data can be written to the Mail2 Register using B0-B17 (B18-B35 are don't care inputs). In this first case A0-A17 will have valid data (A18-A35 will be indeterminate) ...

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... IDT723623/723633/723643 BUS-MATCHING SyncFIFO™ 256 x 36, 512 x 36, 1,024 x 36 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1 PZL t PLZ Low-Level Output t PZH High-Level Output t PHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTE: 1 ...

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IDT X XXXXXX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. 10/04/2000 pgs. 1 through 28. 03/21/2001 pgs 6 and 7. 08/01/2001 pgs and 28. CORPORATE HEADQUARTERS 2975 Stender Way ...