IDT723642 Integrated Device Technology, Inc., IDT723642 Datasheet

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IDT723642

Manufacturer Part Number
IDT723642
Description
CMOS SyncBiFIFOO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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IDT723642L15PQF
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IDT
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1 500
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Free-running CLKA and CLKB may be asynchronous or
• Two independent clocked FIFOs buffering data in oppo-
• Memory storage capacity:
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• IRA, ORA,
• IRB, ORB,
• Supports clock frequencies up to 67MHz
FUNCTIONAL BLOCK DIAGRAM
COMMERCIAL TEMPERATURE RANGE
1996 Integrated Device Technology, Inc.
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
site directions
Integrated Device Technology, Inc.
A
CLKA
MBF2
W/
MBA
0
RST1
CSA
ENA
ORA
AFA
- A
AEA
R
IRA
FS
FS
A
35
0
1
AEA
AEB
IDT723622–256 x 36 x 2
IDT723632–512 x 36 x 2
IDT723642–1024 x 36 x 2
Control
Port-A
FIFO1,
Mail1
Reset
Logic
Logic
, and
, and
36
AFA
AFB
36
flags synchronized by CLKA
flags synchronized by CLKB
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
9
FIFO 1
CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2,
1024 x 36 x 2
FIFO 2
Pointer
Pointer
Read
Write
Programmable Flag
Offset Registers
Status Flag
Status Flag
1024 x 36
1024 x 36
Register
256 x 36
512 x 36
256 x 36
512 x 36
Register
SRAM
SRAM
Mail 1
Mail 2
Logic
Logic
5.22
Pointer
Pointer
Read
Write
• Fast access times of 11ns
• Available in 132-pin Plastic Quad Flatpack (PQF) or
• Low-power 0.8-Micron Advanced CMOS technology
• Industrial temperature range (-40
DESCRIPTION:
low-power, CMOS Bidirectional SyncFIFO (clocked) memory
which supports clock frequencies up to 67MHz and have read
access times as fast as 11ns. Two independent 256/512/
1024x36 dual-port SRAM FIFOs on board each chip buffer
data in opposite directions. Each FIFO has flags to indicate
empty and full conditions and two programable flags (almost
space-saving 120-pin Thin Quad Flatpack (PF)
able, tested to military electrical specifications
The IDT723622/723632/723642 is a monolithic, high-speed,
36
36
Control
FIFO2,
Mail2
Reset
Logic
Port-B
Logic
o
C to +85
ORB
AEB
B
IRB
AFB
MBF1
0
RST2
CLKB
CSB
W
ENB
MBB
- B
/RB
IDT723622
IDT723632
IDT723642
DECEMBER 1996
35
o
3022 drw 01
C) is avail-
DSC-3022/3

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IDT723642 Summary of contents

Page 1

... Two independent clocked FIFOs buffering data in oppo- site directions • Memory storage capacity: IDT723622–256 IDT723632–512 IDT723642–1024 • Mailbox bypass register for each FIFO • Programmable Almost-Full and Almost-Empty flags • Microprocessor Interface Control Logic AEA AFA • ...

Page 2

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 DESCRIPTION (CONTINUED) Full and almost Empty) to indicate when a selected number of words is stored in memory. Communication between each port ...

Page 3

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 PIN CONFIGURATION ...

Page 4

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port-A Data I/0 AEA Port-A Almost O -Empty Flag (Port A) AEB Port-B Almost O -Empty ...

Page 5

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 PIN DESCRIPTIONS (CONT.) Symbol Name I/O MBB Port-B Mailbox I Select MBF1 Mail1 Register O Flag MBF2 Mail2 Register O Flag ORA ...

Page 6

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UN- LESS OTHERWISE NOTED) Symbol V Supply Voltage Range CC (2) V Input Voltage ...

Page 7

... This is the supply current when each input is at least one of the specified TTL voltage levels rather than -0 CSA = VIH CSB = VIH CSA = VIL CSB = VIL All Other Inputs 5.22 COMMERCIAL TEMPERATURE RANGE IDT723622 IDT723632 IDT723642 Commerical t = 15, 20 (1) Min. Typ. Max. 2.4 0 400 A0-A35 0 B0-B35 0 A0-A35 1 B0- ...

Page 8

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPER- ATING FREE-AIR TEMPERATURE Symbol Parameter f Clock Frequency, CLKA or CLKB S ...

Page 9

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, C Symbol Parameter t Access Time, CLKA to A0-A35 and ...

Page 10

... Valid programming values for the registers ranges from 1 to 252 for the IDT723622 508 for the IDT723632; and 1 to 1020 for the IDT723642. After all the offset registers are programmed from port A, the port-B input- ready flag (IRB) is set HIGH, and both FIFOs begin normal operation ...

Page 11

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 port-B operation. The port-B control signals are identical to those of port A with the exception that the port-B write/read select ( ...

Page 12

... X1 (X1+1) to [1024-(Y1+1)] (1024-Y1) to 1023 512 1024 Table 4. FIF01 Flag Operatlon AEB . Y1 is the almost-full offset for FIFO1 used by (1,2) IDT723642 (1, (X2+1) to [1024-(Y2+1)] (1024-Y2) to 1023 512 1024 Table 5. FIF02 Flag Operatlon AEA . Y2 is the almost-full offset for FIFO2 used by 5.22 ...

Page 13

... An almost-full flag is HIGH when the number of words in its FIFO is less than or equal to [256-(Y+1)], [512- (Y+1)], or [1024-(Y+1)] for the IDT723622, IDT723632, or IDT723642 respectively. Note that a data word present in the or greater FIFO output register has been read from memory. SKEW1 ...

Page 14

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKA CLKB t RSTS RST1 FS1,FS0 IRA ORB t RSF AEB t RSF AFA t RSF MBF1 Figure 1. FIFO1 Reset Loading ...

Page 15

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLK t t CLKH CLKL CLKA IRA t ENS CSA t ENS ENS MBA t ENS ENA ...

Page 16

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLK t t CLKH CLKL CLKB ORB CSB W /RB MBB ENB t MDV B35 NOTE: 1. ...

Page 17

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKA CSA LOW HIGH t t ENS ENH MBA t t ENS ENH ENA HIGH ...

Page 18

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKB CSB LOW W LOW / ENS MBB t ENS ENB HIGH IRB B35 W1 ...

Page 19

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLK t t CLKH CLKL CLKB CSB LOW W HIGH /RB MBB LOW t ENS ENB HIGH ORB B0 -B35 Previous ...

Page 20

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLK t t CLKH CLKL CLKA CSA LOW LOW MBA LOW t ENS ENA HIGH ORA A0 -A35 ...

Page 21

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKB t t ENH ENS ENB t SKEW2 CLKA AEA X2 Words in FIFO2 ENA NOTES the minimum time ...

Page 22

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKB t ENS ENB AFB [D-(Y2+1)] Words in FIFO2 CLKA ENA NOTES the minimum time between a rising CLKB ...

Page 23

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 CLKB CSB W /RB MBB ENB B0 - B35 CLKA MBF2 CSA MBA ENA A35 ...

Page 24

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 300 f = 1/2 f data 0pF L 250 200 150 100 ...

Page 25

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 PARAMETER MEASUREMENT INFORMATION From Output Under Test Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS ...

Page 26

IDT723622/723632/723642 CMOS SyncBiFIFO 256 512 1024 ORDERING INFORMATION IDT XXXXXX X XX Device Type Power Speed X X Package Process/ Temperature Range BLANK Commercial ( +70 ...

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