IDT723644 Integrated Device Technology, Inc., IDT723644 Datasheet
IDT723644
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IDT723644 Summary of contents
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... Programmable Flag Timing Offset Registers Mode FIFO2 Status Flag Logic Read Write Pointer Pointer RAM ARRAY 256 512 x 36 1,024 x 36 Mail 2 Register 1 IDT723624 IDT723634 IDT723644 MBF1 36 EFB/ORB AEB FWFT FFB/IRB AFB 36 FIFO2, MRS2 Mail2 Reset PRS2 Logic CLKB CSB W/RB ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 The IDT723624/723634/723644 is a monolithic, high-speed, low- power, CMOS bidirectional synchronous (clocked) FIFO memory which supports clock frequencies up to ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox register width matches the selected Port ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 Symbol Name I/O A0-A35 Port A Data I/O 36-bit bidirectional data port for side A. AEA Port A Almost- O ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 Symbol Name I/O FS1/SEN Flag Offset I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During ...
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... CC 6 COMMERCIAL TEMPERATURE RANGE Commercial Unit –0 –0 +0 –0 +0 ±20 mA ±50 mA ±50 mA ±400 mA –65 to 150 IDT723624 IDT723634 IDT723644 Commercial t = 12, 15ns CLK Min. Typ. (2) Max. Unit 2.4 — — — — 0.5 — — ±10 — — ±10 — — 8 — ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously ...
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... Requirement to count the clock edge as one of at least four needed to reset a FIFO. 3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. 4. Design simulated, not tested. COMMERCIAL TEMPERATURE RANGE Commercial IDT723624L12 IDT723624L15 IDT723634L12 IDT723634L15 IDT723644L12 IDT723644L15 Min. Max. — ...
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... Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH. 3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. (2) (3) and CLKB to A0-A35 9 COMMERCIAL TEMPERATURE RANGE Commercial IDT723624L12 IDT723624L15 IDT723634L12 IDT723634L15 IDT723644L12 IDT723644L15 Min Max. Min. Max . Unit ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 MASTER RESET (MRS1, MRS2) After power up, a Master Reset operation must be performed by providing a LOW pulse to ...
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... Valid programming values for the registers range from 1 to 252 for the IDT723624 508 for the IDT723634; and 1 to 1,020 for the IDT723644. After all the offset registers are programmed from Port A, the Port B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal operation ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 impedance state when either CSA or W/RA is HIGH. The A0-A35 lines are active outputs when both CSA and W/RA ...
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... IDT723644 (X1+1) to [1,024-(Y1+1)] (1,024-Y1) to 1,023 512 1,024 (1,2) (3) (3) IDT723644 (X2+1) to [1,024-(Y2+1)] (1,024-Y2) to 1,023 512 1,024 13 COMMERCIAL TEMPERATURE RANGE Synchronized Synchronized to CLKB to CLKA EFB/ORB AEB ...
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... HIGH when the number of words in its FIFO is less than or equal to [256- (Y+1)], [512-(Y+1)], or [1,024-(Y+1)] for the IDT723624, IDT723634, or IDT723644 respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for its Almost-Full flag to reflect the new level of fill ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a Port A read is ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 BYTE ORDER ON PORT SIZE BYTE ORDER ON PORT SIZE H ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA CLKB t RSTS MRS1 BE/FWFT SPM FS1,FS0 FFA/IRA EFB/ORB t RSF AEB t RSF AFA t RSF MBF1 NOTES: ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA 1 4 MRS1, MRS2 t FSS t FSH SPM t FSS t FSH 0,0 FS1,FS0 FFA/IRA ENA A0-A35 CLKB ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB FFB/IRB HIGH CSB W/RB MBB ENB B0-B17 (1) SIZE MODE BM SIZE ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t CLKH CLKB EFB/ORB HIGH CSB W/RB MBB ENB t EN B0-B35 (Standard Mode B0-B35 ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB EFB/ORB HIGH CSB W/RB MBB t ENS2 ENB t MDV t EN B0-B8 (Standard Mode) t MDV OR t ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA CSA LOW WRA HIGH t ENS2 MBA t ENS2 ENA IRA HIGH t DS A0-A35 W1 t SKEW1 CLKB ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKA CSA LOW WRA HIGH t t ENS2 MBA t t ENS2 ENA FFA HIGH A0-A35 W1 ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENS2 ENH ENB FFB HIGH ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB ORB HIGH B0-B35 Previous ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB EFB HIGH B0-B35 Previous ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA ORA HIGH A0-A35 Previous ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH A0-A35 Previous ...
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... FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO Maximum FIFO Depth = 256 for the IDT723624, 512 for the IDT723634, 1,024 for the IDT723644. ...
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... FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO Maximum FIFO Depth = 256 for the IDT723624, 512 for the IDT723634, 1,024 for the IDT723644. ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 CLKB t ENS1 CSB t ENS1 W/RB t ENS2 MBB t ENS2 ENB B0-B35 CLKA MBF2 CSA W/RA MBA ENA ...
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IDT723624/723634/723644 CMOS SyncBiFIFO™ WITH BUS-MATCHING 256 512 1,024 PARAMETER MEASUREMENT INFORMATION From Output Timing 1.5 V Input Data, 1.5 V Enable Input VOLTAGE WAVEFORMS SETUP ...
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IDT X XX XXXXXX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. 10/04/2000 pgs. 1 through 35, except pgs. 20, 24-26, 32 and 33. 03/22/2001 pgs. 6 and 7. 08/01/2001 pgs ...