IDT77105 Integrated Device Technology, Inc., IDT77105 Datasheet
IDT77105
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IDT77105 Summary of contents
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... Description Description Description Description The IDT77105 is a member of IDT's family of products developed to support Asynchronous Transfer Mode (ATM) data communications and networking. The IDT77105 provides the Transmission Convergence (TC) and (PMD) layers of a 25.6 Mbps ATM PHY suitable for ATM networks using Unshielded Twisted Pair (UTP) Category 3 (or better) wiring ...
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... IDT77105 Pin Configurations Pin Configurations Pin Configurations Pin Configurations RDB LL_F ilter_2 LL_F ilter_1 Index M ark TXENB TXFULL RXENB 344 September 11, 2000 ...
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... IDT77105 Package Dimensions Package Dimensions Package Dimensions Package Dimensions 64 1 64-Pin STQFP PP64 D1 4.3021 ' D 5.3521 ' Draft Angle = 11° - 13° 0.20 Rad Typ 5.4035 ' 4.3514 ' 4° ± 4° A 2.4792 ' L b Dimensions Dimensions Dimensions Dimensions Dimension Letter Tolerance (mm) Dimension (mm) A Max. A1 ±.05 A2 ± ...
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... Output Low Current for Transmit Line Signal Z Output Impedance OUT Input Parameters for IDT77105 Receive Line Signal Input Parameters for IDT77105 Receive Line Signal Input Parameters for IDT77105 Receive Line Signal Input Parameters for IDT77105 Receive Line Signal Symbol I Input Leakage Current LI C Input Capacitance IN 1 ...
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... IDT77105 Pin Name I/O Interfaces to 22 RxSOC O UTOPIA bus 23 RxEmpty/RxClav O UTOPIA bus 24 RxRef O UTOPIA bus 25 V — Power plane CC 26 RxData0 O UTOPIA bus 27 RxData1 O UTOPIA bus 28 RxData2 O UTOPIA bus 29 RxData3 O UTOPIA bus 30 RxData4 O UTOPIA bus 31 RxData5 O UTOPIA bus 32 GND — Ground plane ...
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... Communications Standard 25MbpsATM Communications Standard 25MbpsATM Communications Standard The IDT77105 implements the physical layer standard for 25.6Mbps ATM network communications. The physical layer is divided into a Phys- ical Media Dependent sub layer (PMD) and Transmission Convergence (TC) sub layer. The PMD sub layer includes the functions for the trans- mitter, receiver, and timing recovery that allow connection to transmis- sion media conforming to TIA/EIA 568 (UTP Category 3) ...
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... The symbols are then sent to the 5b/4b decoder, followed by the Command Byte Interpreter, De-Scram- bler, and finally the UTOPIA interface to the outside world. Note that although the IDT77105 can detect symbol and HEC errors, it does not attempt to correct them. Data ...
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... UTOPIA Interface UTOPIA Interface UTOPIA Interface The 'UTOPIA' (Universal Test & Operations PHY Interface for ATM) interface is used as the data path interface between the IDT77105 PHY and other system elements such as the Segmentation and Reassembly (SAR) device, or switching systems. Overview Overview ...
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... IDT77105 Transmit Interface Transmit Interface Transmit Interface Transmit Interface Signals TxData[7:0], TxParity—Transmit Data. TxData[7] is the MSB. TxSOC—Start Of Cell. Active high signal to be asserted when TxData contains the first byte of the cell. TxENB—Enable. Active low signal to be asserted when TxData contains valid data. TxFull/TxClav— ...
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... IDT77105 TxClk TxSOC TxClav TxEnb TxData P48 TxClk TxData P44 P45 TxFul l / TxClav TxEnb RxClk RxSOC R xEm pt y/RxClav RxEnb RxData RxClk RxSOC R xEm pt y/ RxClav R xEnb RxData P44 P45 Figure 4 Transmit Waveform for Cell-Level Handshake P46 P47 P48 Figure 5 TxFull/TxClav Waveform ...
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... Control and Status Interface Control and Status Interface The Control and Status Interface provides the data and control pins needed to set and reset registers within the IDT77105. Registers are used to set desired operating characteristics and functions, and to communicate status to external systems. ...
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... Establishment Establishment Establishment During the initial state of connecting the line for IDT77105, there are some interrupts (“HEC Error Cell Received” interrupt, “Short Cell Received” interrupt, and “Received Cell Symbol Error” interrupt) that may appear. These interrupts should be masked. ...
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... Receive HEC Error Counter ! – 5 bit counter – counts all received HEC errors IDT77105 25 Mbps TC Figure 9 Normal Mode IDT77105 25 Mbps TC Figure 10 PHY Loopback IDT77105 25 Mbps TC Figure 11 Line Loopback PMD Line Interface 3445 drw 12 PMD Line Interface ...
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... IDT77105 The TxCell and RxCell counters are sized (16 bits) to provide a full cell count (without roll over) if the counter is read once/second. The Symbol Error counter and HEC Error counter were given sufficient size to indicate exact counts for low error-rate conditions. If these counters overflow, a gross condition is occurring, where additional counter resolu- tion does not provide additional diagnostic benefit ...
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... IDT77105 RxClk RxSOC Z RxClav RxEnb RxData PHY to Magnetics interface PHY to Magnetics interface PHY to Magnetics interface PHY to Magnetics interface Figure 21 provides the appropriate connection scheme to the Magnetics Module. The set of values provided will ensure the return Loss specifica- tion is met. Status and Control Register List ...
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... IDT77105 Interrupt Status Interrupt Status Interrupt Status Interrupt Status Address: 0x01 Address: 0x01 Address: 0x01 Address: 0x01 Master Type Initial State Bit 7 — — Reserved Bit Bad Signal Good Signal Bit See definition on pages 10 and 11 Good Signal 0 = Bad Signal Bit 5 sticky ...
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... IDT77105 LED Driver and HEC Status/Control LED Driver and HEC Status/Control LED Driver and HEC Status/Control LED Driver and HEC Status/Control Address: 0x03 Address: 0x03 Address: 0x03 Address: 0x03 Master Type Initial State Bit 7 0 Reserved Bit 6 R enable Disable Receive HEC Checking (HEC Enable) ...
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... IDT77105 LED Output LED Output LED Output LED Output LED outputs are able to source and sink current, to enable driving two-color LEDs. The Tx and Rx LEDs are driven according to the following table: AC Test Conditions AC Test Conditions AC Test Conditions AC Test Conditions TxCLK TxData [7:0] ...
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... IDT77105 UTOPIA Bus Timing Parameters UTOPIA Bus Timing Parameters UTOPIA Bus Timing Parameters UTOPIA Bus Timing Parameters Symbol t1 RxEnb set up time to RxCLK t2 RxEnb hold time from RxCLK t3 tPD from RxCLK to RxSOC, RxData, and RxRef t4 RxEmpty delay from RxCLK t5 TxData[7:0], TxParity setup time to TxCLK ...
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... IDT77105 TxOSC R ESET ADDR/DATA (input) ALE ADDR/DATA (output) Utility Bus Read Cycle Utility Bus Read Cycle Utility Bus Read Cycle Utility Bus Read Cycle Name Min. Max. Unit Tas 10 — ns Tcsrd 0 — ns Tah 5 — ns Tapw 10 — ns Ttria — Trdpw 20 — ns Tdh 0 — ...
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... Schematic for ATM User Schematic for ATM User Schematic for ATM User Note configure for ATM network, refer to Figure 23. 2. Only the analog pins are shown on the IDT77105 should be TDK-NLC1210-3R3M or equivalent. Tas Tah Address Tapw Tcswr Figure 20 Utility Bus Write Cycle GND ...
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... IDT77105 Analog Component Values Analog Component Values Analog Component Values Analog Component Values Component Value 267 5100 R7 2000 R10 82 C1 .1µF C2 120pF C3 120pF C4 470pF C5 47 0pF L1 3.3µH PC Board Layout for ATM Network PC Board Layout for ATM Network PC Board Layout for ATM Network ...
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... IDT77105 PC Board Layout for ATM User PC Board Layout for ATM User PC Board Layout for ATM User PC Board Layout for ATM User Note RJ45 Connector Note 3 Note power of ground plane inside this area. 2.Dotted signal traces (Tx) should be run on the back side of the PC Board. ...
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... IDT77105 Ordering Information Ordering Information Ordering Information Ordering Information IDT NNNNN A Device Type Power Revision History Revision History Revision History Revision History 9/8/95: Initial Draft 9/13/95: Revision 9/21/95: Revision 10/30/05: Corrected Typographical Errors 11/13/95: Corrected Vcc and GND nomenclature and Figure 10 ...