AD9873JS Analog Devices, AD9873JS Datasheet
AD9873JS
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AD9873JS Summary of contents
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... TxDAC registered trademark of Analog Devices, Inc. Analog Front End Converter for Set-Top Box, Cable Modem FUNCTIONAL BLOCK DIAGRAM COS ...
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AD9873 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL ...
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V SPECIFICATIONS 4), ADC Sample Rate derived from PLL f Parameter SYSTEM CLOCK, DAC SAMPLING f Frequency Range OSC IN and XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Capacitance Input Resistance ...
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AD9873–SPECIFICATIONS Parameter 8-BIT ADC CHARACTERISTICS (Continued) Dynamic Performance (A = –0 MHz) IN Effective Number of Bits (ENOB) 2 Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious Free Dynamic Range ...
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Parameter 12-BIT ADC CHARACTERISTICS (Continued) Dynamic Performance (A = –0 MHz) IN Signal-to-Noise and Distortion Ratio (SINAD) Signal-to-Noise and Distortion Ratio (SINAD) Effective Number of Bits (ENOB) 3 Effective Number of Bits (ENOB) Signal-to-Noise Ratio ...
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AD9873–SPECIFICATIONS Parameter CMOS LOGIC INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance CMOS LOGIC OUTPUTS (1 mA Load) Logic “1” Voltage Logic “0” Voltage POWER SUPPLY Analog Supply Current I AS Digital Supply ...
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... Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. Model AD9873JS AD9873-EB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9873 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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AD9873 DEFINITIONS OF TERMS DIFFERENTIAL NONLINEARITY ERROR (DNL, NO MISSING CODES) An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that ...
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PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Pin Function 1, 84, 87 AVDD Analog Supply Voltage 92, 95 10-/12-Bit ADC 2, 21, 70 DRGND Pin Driver Digital Ground 3, 22, 72 DRVDD Pin Driver Digital Supply Voltage 4–15 IF11–IF0 Multiplexed Output ...
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AD9873 AVDD DRGND DRVDD (MSB) IF(11) IF(10) IF(9) IF(8) IF(7) IF(6) IF(5) IF(4) IF(3) IF(2) IF(1) IF(0) ( MSB) RxIQ(3) RxIQ(2) RxIQ(1) RxIQ(0) RxSYNC DRGND DRVDD MLCK DVDD DGND TxSYNC (MSB) TxIQ(5) TxIQ(4) TxIQ(3) TxIQ(2) PIN CONFIGURATION 1 PIN 1 ...
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Address (Hex) Bit 7 Bit 6 Bit 5 RESET 00 SDIO LSB/MSB Bidirectional First 01 PLL OSC IN MCLK Lock Divider Divider Detect (4) R <5> 02 Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down Power-Down 00 PLL ...
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AD9873 REGISTER BIT DEFINITIONS 00h, Bits 0–4: OSC IN Multiplier–Register Address This register field is used to program the on-chip multiplier (PLL) that generates the chip’s high-frequency system clock, f For example, to multiply the external crystal clock f decimal, ...
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Bit 4, Bit 5: Profile Select The AD9873 quadrature digital upconverter is capable of storing four preconfigured modulation modes called profiles that define a transmit frequency tuning word and cable driver amplifier con- trol. Profile Select bits <1:0> or ...
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AD9873 Typical Performance Characteristics [ 4], ADC Sample Rate derived directly from f TYPICAL POWER CONSUMPTION CHARACTERISTICS (20 MHz Single Tone, unless otherwise noted) 380 360 340 320 300 280 260 240 220 200 120 140 ...
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SINGLE SIDEBAND TRANSMIT SPECTRUM 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 FREQUENCY – MHz ...
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AD9873 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 FREQUENCY OFFSET – MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –50 –40 –30 –20 – ...
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AD9873 ...
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AD9873 TYPICAL ADC PERFORMANCE CHARACTERISTICS (ADC Sample Rate derived directly from f 27 MHz [13.5 MSPS for 8-bit ADCs], Single-Tone 5 MHz Input Signal, unless otherwise noted.) 70 12-BIT ADC 65 10-BIT ADC 8-BIT ADC 45 0 ...
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FREQUENCY – MHz 0 –5 –25 –45 –65 –85 –105 –125 FREQUENCY – MHz 0 –5 –25 –45 –65 –85 ...
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AD9873 THEORY OF OPERATION To gain a general understanding of the AD9873 it is helpful to refer to Figure 1, which displays a block diagram of the device DATA ASSEMBLER HALF-BAND FILTER # SYNC ...
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Transmit Section Modulation Mode Operation The AD9873 accepts 6-bit words, which are strobed synchronous to the master clock MCLK into the Data Assembler. Tx SYNC signals the start of a transmit symbol. Two successive 6-bit words form a 12-bit symbol ...
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AD9873 Digital 8-bit ADC outputs are multiplexed to one 4-bit bus, clocked by a frequency ( four times the sampling rate MCLK whereas the 10- and 12-bit ADCs are multiplexed together to one 12-bit bus clocked by f ...
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PROGRAMMABLE CLOCK OUTPUT REF CLK The AD9873 provides a frequency programmable clock output REF CLK (Pin 71). MCLK (f ) and the master clock divider MCLK ratio R stored in register address 01h determine its frequency ...
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AD9873 Serial Interface Port Pin Description SCLK—Serial Clock. The serial clock pin is used to synchronize data to and from the AD9873 and to run the internal state machines. SCLK maximum frequency is 15 MHz. All data input to the ...
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MCLK Tx SYNC TxI[11: The I/Q sample rate f puts a bandwidth limit on the maxi- IQCLK mum transmit spectrum. This is the familiar Nyquist limit and is equal to one-half f which hereafter will be referred to ...
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AD9873 If a particular application requires an value between 0.45 and 1, the user must oversample the baseband data by at least a factor of four –10 –20 –30 –40 –50 –60 –70 –80 0 0.1 0.2 0.3 ...
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FREQUENCY RELATIVE TO I/Q NYQ. BW Inverse SINC Filter (ISF) The AD9873 transmit section is almost entirely digital. The input “signal” is made up of ...
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AD9873 Signal Level Considerations The quadrature modulator itself introduces a maximum gain signal level. To visualize this, assume that both the I data and Q data are fixed at the maximum ...
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A relatively inexpensive fifth order elliptical low-pass filter is sufficient to suppress the aliased components for HFC network ...
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AD9873 RECEIVE PATH (Rx) ADC Theory of Operation The AD9873’s analog-to-digital converters implement pipelined multistage architectures to achieve high sample rates while con- suming low power. Each ADC distributes the conversion over several smaller ADC subblocks, refining the conversion with ...
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... When dc-coupling is required, op amps’ headroom constraints (such as rail-to-rail op amps) or ones where larger supplies can be used, should be considered. Analog Devices offers differential output operational amplifiers like the AD8131 or AD8132. They can be used for differential or single-ended-to-differential signal conditioning with 8-bit performance to directly drive ADC inputs ...
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AD9873 AVDD 1 2 DRGND DRVDD 3 0.1 F (MSB) IF(11) 4 IF(10) 5 IF(9) 6 IF(8) 7 IF(7) 8 IF(6) 9 IF(5) 10 IF(4) 11 IF(3) 12 IF(2) 13 IF(1) 14 IF(0) 15 (MSB) Rx IQ( IQ(2) ...
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EVALUATION BOARD Hardware The AD9873- evaluation board for the AD9873 analog front end converter. Careful attention to layout and circuit design allow the user to easily and effectively evaluate the AD9873 in any application where high-resolution, and high-speed ...
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OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 100-Lead Metric Quad Flatpack (MQFP) (S-100C) 0.921 (23.4) 0.906 (23.0) 0.791 (20.10) 0.134 0.787 (20.00) (4.30) 0.783 (19.90) MAX 0.742 (18.85) TYP 80 81 0.486 TOP VIEW (12.35) (PINS DOWN) TYP PIN ...