ADUC845 Analog Devices, ADUC845 Datasheet
ADUC845
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ADUC845 Summary of contents
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... Transmitters Data Logging Precision System Monitoring FUNCTIONAL BLOCK DIAGRAM system, provided that the system Embedded 62kB FLASH MCU One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved ADuC845 www.analog.com ...
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... ADuC845 UNITS CONDITION Hz On Both Channels Bits 19.79Hz Update Rate Bits Pk-Pk Range = ± 20mV, 20Hz Update Rate Bits Pk-Pk Range = ± 2.56V, 20Hz Update Rate Bits Pk-Pk Range = ± 2.56V, 59.4Hz Update Rate ...
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... Range pA/V/° µA/V Both ADCs Enabled nA/V/°C V NOXREF bit active if VREF<0.3V NOXREF bit Inactive if VREF>0.65 dBs @DC, AIN=1V, Range=± 2.56V dBs 50/60Hz ± 1Hz, AIN=1V, Range=± 2.56V dBs 50/60Hz ± 1Hz, 59.4 Hz Update Rate ADuC845 ...
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... AIN=1V, Range=± 2.56V dBs 50/60Hz ± 1Hz, 19.79Hz Update Rate dBs 50/60Hz ± 1Hz, 19.79Hz Update Rate V Vref=REFIN(+)-REFIN(-) (or Int 1.25V Ref) V Vref=REFIN(+)-REFIN(-) (or Int 1.25V Ref) nA/V pA/V/°C nA/V ± 2.56V Range pA/V/°C V ADuC845 ...
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... -0.6 V GND DD -5- ADuC845 CONDITION DACCON DACCON From DAC Output to AGND From DAC Output to AGND Guaranteed 12-Bit Monotonic AV Range DD V Range REF Setling time to 1LSB of final value 1 LSB change at major carry initial tolerance @ 25°C, VDD=5V initial tolerance @ 25° ...
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... V 2.4 V 0.8 V 0.8 V 0.8 V +/-10 µ -6- ADuC845 CONDITION Four Trip Points selectable in this range T = 85°C MAX T = 125°C MAX Four Trip Points selectable in this range T = 85°C MAX T = 125°C MAX ...
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... ADuC845 CONDITION Controlled via WDCON SFR PLLCON PLLCON 4.75V < DVDD <5.25V, AVDD= 5.25V core clock = 1.57MHz core clock = 12.58MHz T = 85°C; Osc ON;TIC ON MAX T = 125°C; Osc ON; TIC ON MAX T = 85°C; Osc OFF ...
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... In bipolar mode, the Auxiliary ADC can only be driven to a minimum of AGND – indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar range is still –VREF to +VREF; however, the negative voltage is limited to –30 mV. 12 The ADuC845BCP (CSP Package) has been qualified and tested with the base of the CSP Package floating. 13 Pins configured in SPI Mode, pins configured as digital inputs during this test. ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 AGND and DGND are shorted internally on the ADuC845. 3 Applies to P1.0 to P1.7 pins operating in analog or digital input modes REV. PrB 1 – ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC845 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... AIN7. One or Both current sources can also be configured at this pin. P1.0 has no digital output driver. It can function as a digital input for which ‘0’ must be written to the port bit digital input, this pin must be driven high or low externally. -11- ADuC845 ...
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... I/O Serial data pin for the I pull-up present unless it is outputting logic low. -12- ADuC845 2 C interface input this pin has a weak internal ...
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... External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F7FFh. No external program memory access is available on the ADuC845. To determine the mode of code execution, the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle. ...
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... In this application it uses strong internal pull-ups when emitting 1s. DETAILED BLOCK DIAGRAM WITH PIN NUMBERS Pin numbers refer to the 52pin MQFP package. Figure 1: Detailed Block Diagram of the ADuC845 -14- ADuC845 ...
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... SFR address space are not implemented; i.e., no register exists at this location unoccupied location is read, an unspecified value is returned. SFR locations that are reserved for future use are shaded (RESERVED) and should not be accessed by user software. REV. PrB Figure 6: Complete SFR Map -15- ADuC845 ...
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... Preliminary Technical Data INTRODUCTION The ADuC845 is a 12.58MIPs 8052 core upgrade to the ADuC834. It includes additional analog inputs for applications requiring more ADC channels. It has all the same features as the ADuC834 but the standard 12-cycle 8052 core has been replaced with a 12.58MIPs single cycle core ...
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... Move register to A MOV A,@Ri Move indirect memory to A MOV Rn,A Move A to register MOV @Ri,A Move A to indirect memory MOV A,dir Move direct byte to A MOV A,#data Move immediate to A REV. PrB TABLE IV: Optimized Single Cycle 8051 Instruction Set -17- ADuC845 Bytes Cycles ...
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... One cycle is one clock. 2. MOVX instructions are four cycles when they have 0 wait state. Cycles of MOVX instructions are cycles when they have n wait states. 3. LCALL instruction are three cycles when the LCALL instruction comes from an interrupt. REV. PrB -18- ADuC845 Bytes Cycles 2 2 ...
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... By default the stack will operate exactly like an 8052 in that it will rollover from FFh to 00h in the general purpose RAM. On the ADuC845 however it is possible (by setting CFG845.7) to enable the 11-bit extended stack pointer. In this case the stack will rollover from FFh in RAM to 0100h in XRAM. ...
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... Figure 4. Extended Stack Pointer Operation External Data Memory (External XRAM) Just like a standard 8051 compatible core the ADuC845 can access external data memory using a MOVX instruction. The MOVX instruction automatically outputs the various control strobes required to access the data memory. ...
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... No -21- ADuC845 AFhH 00H No Name Description EXSP Extended SP Enable. If this bit is set to 1 then the stack will rollover from SPH/SP = 00FFh to 0100h. If this bit is cleared to 0 then the SPH SFR will be disabled and the stack will rollover from SP=FFh to SP =00h ...
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... The cut-off frequency and decimated output data rate of the filter are programmable via the SF word loaded in the TABLE V: Typical Output rms noise (µV) vs Input Range and Update Rate for the ADuC845 with chopping Enabled. SF Data Update ...
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... Preliminary Technical Data TABLE VI : Peak to Peak Resolution (bits) vs Input Range and Update Rate for the ADuC845 with chopping Enabled SF Data Update Word Rate (Hz) ± 105. 19.79 13.5 255 5.35 14 Signal Chain Overview (CHOP Disabled, CHOP = 1) With CHOP =1 chopping is disabled. With chopping disabled the available output rates vary from 16 ...
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... Preliminary Technical Data TABLE VII: Typical Output rms noise (µV) vs Input Range and Update Rate for the ADuC845 with chopping disabled. SF Data Update Word Rate (Hz) ± 1365.0 2.47 69 59.36 0.961 255 16.06 0.475 TABLE VIII: Peak to Peak Resolution (bits) vs Input Range and Update Rate for the ADuC845 with chopping disabled. ...
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... REFIN+/- and/or REFIN2+/- inputs would not be recommended in this type of configuration. Burnout Current Sources The Primary ADC on the ADuC845 incorporates two 200uA constant current generators, one sourcing current from the AV AIN(+), and one sinking current from AIN(-) to AGND. These currents are only configurable for use on AIN4 → AIN5 and/or AIN6 → ...
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... After a calibration, this bit also flags error conditions that caused the calibration registers not to be written. Cleared by a write to the mode bits to initiate a conversion or calibration. 2 ERR1 Auxiliary ADC Error Bit. Same definition as ERR0 referred to the Auxiliary ADC. 1 ––– Reserved for Future Use 0 ––– Reserved for Future Use REV. PrB -26- ADuC845 ...
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... User should connect system zero-scale input to the enabled ADC input(s) as selected by CH3-CH0 and ACH3-ACH0 bits in the ADC0CON2 and ADC1CON Registers. User should connect system full-scale input to the enabled ADC input(s) as selected by CH3-CH0 and ACH3-ACH0 bits in the ADC0CON2 and ADC1CON Registers. -27- ADuC845 ...
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... Selected Primary ADC Input Range (VREF = 2 ± mV– Unipolar Mode) 1 ± mV– Unipolar Mode) 0 ± mV– Unipolar Mode) 1 ±160 mV (0 mV–160 mV in Unipolar Mode) 0 ±320 mV (0 mV–320 mV in Unipolar Mode) 1 ±640 mV (0 mV–640 mV in Unipolar Mode) 0 ±1. V–1. Unipolar Mode) 1 ±2. V–2. Unipolar Mode) -28- ADuC845 ...
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... AINCOM (CSP package only). Not a valid selection on MQFP package AIN9 AINCOM (CSP package only). Not a valid selection on MQFP package AIN0 AIN1 1 1 AIN2 AIN3 0 0 AIN4 AIN5 0 1 AIN6 AIN7 1 0 AIN8 AIN9 (CSP package only). Mot a valid selection on MQFP package AINCOM AINCOM -29- ADuC845 ...
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... AIN8 AINCOM (CSP package only). Not a valid selection on MQFP package 0 1 AIN9 AINCOM (CSP package only). Not a valid selection on MQFP package 1 0 AIN0 AIN1 1 1 AIN2 AIN3 0 0 AIN4 AIN5 0 1 AIN6 AIN7 1 0 TEMPERATRE SENSOR 1 1 AINCOM AINCOM -30- ADuC845 ...
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... C serial interface. The the user and is not multiplexed with any other I/O functionality on the chip. This means that on the ADuC845 the I interfaces can be used at the same time. When using the I SPI interfaces simultaneously, because they both utilize the same interrupt routine (vector address 0x3B), when an interrupt occurs ...
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... The Slave Select (SS) input pin is only used when the ADuC834 is configured in SPI Slave mode. This line is active low. Data is only received or transmitted in Slave mode when the SS pin is low, allowing the ADuC845 to be used in single master, multislave SPI configurations. If CPHA = 1, the SS input may be permanently pulled low. ...
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... C utilize the same ISR (Vector address 0x3B), therefore when using both SPI & I check the interfaces following an interrupt to determine which one caused the interrupt. REV. PrB Selected Bit Rate f /2 core f /4 core f /8 core f /16 core -33- ADuC845 2 C simultaneously it will be necessary to ...
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... Preliminary Technical Data REV. PrB OUTLINE DIMENSIONS -34- ADuC845 ...