ADSP-21262 Analog Devices, ADSP-21262 Datasheet
ADSP-21262
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ADSP-21262 Summary of contents
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... On-chip memory—2M bits of on-chip SRAM and a dedicated 4M bits of on-chip mask-programmable ROM Six independent synchronous serial ports provide a variety of serial communication protocols including TDM and I modes The ADSP-21262 is available with a 200 MHz core instruction rate. For complete ordering information, see Guide on Page DUAL PORTED MEMORY INSTRUCTION ...
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... ADSP-21262 KEY FEATURES At 200 MHz (5 ns) core instruction rate, the ADSP-21262 operates at 1200 MFLOPS peak/800 MFLOPS sustained performance whether operating on fixed or floating point data 400 MMACS sustained performance at 200 MHz Super Harvard Architecture—three independent buses for dual data fetch, instruction fetch, and nonintrusive, zero- ...
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... Single-Cycle Fetch of Instruction and Four Operands ..5 Instruction Cache ...............................................5 Data Address Generators With Zero-Overhead Hardware Circular Buffer Support .......................5 Flexible Instruction Set ........................................6 ADSP-21262 Memory and I/O Interface Features ..........6 Dual-Ported On-Chip Memory ..............................6 DMA Controller .................................................6 Digital Audio Interface (DAI) ................................6 Serial Ports ........................................................6 Serial Peripheral (Compatible) Interface ...................8 Parallel Port ...
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... Many other SRU configurations are possible 2.5 ns ADSP-21262 FAMILY CORE ARCHITECTURE 10 ns The ADSP-21262 is code compatible at the assembly level with the ADSP-21266, ADSP-21160 and ADSP-21161, and with the 22.5 ns first generation ADSP-2106x SHARC DSPs. The ADSP-21262 40 ns shares architectural features with the ADSP-2126x and ...
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... Data Address Generators with Zero-Overhead Hardware Circular Buffer Support The ADSP-21262’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buffers allow efficient program- ming of delay lines and other data structures required in digital signal processing, and are commonly used in digital filters and Rev ...
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... IDP (Input Data Port), Parallel Data Acquisition Port (PDAP), or the parallel port. Twenty-two channels of DMA are available on the ADSP-21262—one for the SPI interface, 12 via the serial ports, eight via the Input Data Port, and one via the processor’s parallel port. Programs can be downloaded to the ADSP-21262 using DMA transfers ...
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... GENERATES ADDRESS WITHIN THE 0x0016 0000 RANGE 0x0000 0000-0x00FF FFFF. 0x0017 FFFF 0x0018 0000 0x0018 FFFF 0x0019 0000 - 0x001D FFFF 0x001E 0000 0x001F FFFF Figure 3. ADSP-21262 Memory Map Rev Page May 2004 ADSP-21262 ADDRESS 0x0020 0000 RESERVED 0x00FF FFFF 0x0100 0000 EXTERNAL DMA ...
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... Latch Enable) pins are the control pins for the parallel port. Timers The ADSP-21262 has a total of four timers: a core timer able to generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be indepen- dently set to operate in one of three modes: • ...
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... VDD TARGET BOARD JTAG EMULATOR CONNECTOR Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149.1 JTAG test access port of the ADSP-21262 processor to monitor and control the target board processor during emulation. Analog Devices DSP Tools product line of JTAG emulators provides emulation at full processor speed, allowing inspection and modification of memory, registers, and processor stacks. The processor’ ...
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... This document is updated regularly to keep pace with improvements to emulator support. ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP-21262 architecture and functionality. For detailed information on the ADSP-2126x family core architecture and instruction set, refer to the ADSP-2126x DSP Core Manual and the ADSP-21160 SHARC DSP Instruction Set Reference ...
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... Power Supply Synchronous, (A/D) = Active Drive, (O/D) = Open Drain, and T = Three-State. Function Parallel Port Address/Data. The ADSP-21262 parallel port and its corresponding DMA unit output addresses and data for peripherals on these multiplexed pins. The multiplex state is determined by the ALE pin. The parallel port can operate in either 8-bit or 16-bit mode ...
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... MOSI output pin of the master and shifted into the MOSI input(s) of the slave(s). MOSI has a 22.5 k internal pull-up resistor. SPI Master In Slave Out. If the ADSP-21262 is configured as a master, the MISO pin becomes a data receive (input) pin, receiving input data. If the ADSP-21262 is configured as a slave, the MISO pin becomes a data transmit (output) pin, trans- mitting output data ...
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... Three-state is a three-state driver. Function Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21262 clock input. It configures the ADSP-21262 to use either its internal clock generator or an external clock source. Connecting the necessary components to CLKIN and XTAL enables the internal clock generator. Connecting the external clock to CLKIN while leaving XTAL unconnected configures the ADSP-21262 to use the external clock source such as an external clock oscillator ...
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... ADSP-21262 ADDRESS DATA PINS AS FLAGS To use these pins as flags (FLAGS15-0) set (=1) Bit 20 of the SYSCTL register and disable the parallel port. Table 3. AD[15:0] to Flag Pin Mapping AD Pin Flag Pin AD0 FLAG8 AD1 FLAG9 AD2 FLAG10 AD3 FLAG11 AD4 FLAG12 AD5 FLAG13 ...
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... ADSP-21262 SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS 1 Parameter V Internal (Core) Supply Voltage DDINT A Analog (PLL) Supply Voltage VDD V External (I/O) Supply Voltage DDEXT V High Level Input Voltage IH V Low Level Input Voltage IL V High Level Input Voltage IH_CLKIN V Low Level Input Voltage IL_CLKIN ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-21262 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Timingrequirements apply to signals that are controlled by cir- cuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Rev Page May 2004 ADSP-21262 ...
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... ADSP-21262 Power-Up Sequencing The timing requirements for DSP startup are given in Table 9. Power-Up Sequencing Timing Requirements (DSP Startup) Parameter Timing Requirements t RESET Low Before V RSTVDD Before V IVDDEVDD DDINT t CLKIN Valid After V CLKVDD t CLKIN Valid Before RESET Deasserted CLKRST t PLL Control Setup Before RESET Deasserted ...
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... CKH Figure 7. Clock Input Clock Signals The ADSP-21262 can use an external clock or a crystal. See CLKIN pin description. The programmer can configure the ADSP-21262 to use its internal clock generator by connecting the necessary components to CLKIN and XTAL. the component connections used for a crystal operating in fun- damental mode ...
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... ADSP-21262 Reset Table 11. Reset Parameter Timing Requirements t RESET Pulse Width Low WRST t RESET Setup Before CLKIN Low SRST 1 Applies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than 100 s while RESET is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator). ...
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... Timing Requirement t Timer[2:0] Pulse Width PWI DAI_P[20:1] (TIMER[2:0]) Min Max 2 t – 1 2(2 CCLK t PWMO Figure 12. Timer[2:0] PWM_OUT Timing Min Max 2 t 2(2 CCLK t PWI Figure 13. Timer[2:0] Width Capture Timing Rev Page May 2004 ADSP-21262 Unit 31 – CCLK Unit 31 – CCLK ...
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... ADSP-21262 DAI Pin to Pin Direct Routing For direct pin connections only (for example DAI_PB01_I to DAI_PB02_O). Table 16. DAI Pin to Pin Routing Parameter Timing Requirement t Delay DAI Pin Input Valid to DAI Output Valid DPIO DAI_Pn DAI_Pm t DPIO Figure 14. DAI Pin to Pin Direct Routing Rev ...
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... All timing param- eters and switching characteristics apply to external DAI pins (DAI_P07 – DAI_P20). t STRIG t HTRIG t DPCGIO t DTRIG Figure 15. Precision Clock Generator (Direct Pin Routing) Rev Page May 2004 ADSP-21262 Min Max 2.5 10 2.5 + 2.5 × 2.5 × t PCGOW PCGOW 40 ...
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... ADSP-21262 Flags The timing specifications provided below apply to the FLAG[3:0] and DAI_P[20:1] pins, the parallel port, and the serial peripheral interface (SPI). See Table 2 on Page 11 more information on flag use. Table 18. Flags Parameter Timing Requirement t FLAG[3:0] IN Pulse Width FIPW Switching Characteristic ...
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... Memory Read—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21262 is accessing external memory space. Table 19. 8-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data [7:0] Setup Before RD High DRS t Address/Data [7:0] Hold After RD High DRH ...
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... ADSP-21262 Table 20. 16-Bit Memory Read Cycle Parameter Timing Requirements t Address/Data [15:0] Setup Before RD High DRS t Address/Data [15:0] Hold After RD High DRH Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW t Address/Data [15:0] Setup Before ALE Deasserted ADAS t Address/Data [15:0] Hold After ALE Deasserted ...
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... Memory Write—Parallel Port Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) when the ADSP-21262 is accessing external memory space. Table 21. 8-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW t Address/Data [15:0] Setup Before ALE Deasserted ...
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... ADSP-21262 Table 22. 16-Bit Memory Write Cycle Parameter Switching Characteristics t ALE Pulse Width ALEW t ALE Deasserted to Read/Write Asserted ALERW t Address/Data [15:0] Setup Before ALE Deasserted ADAS t Address/Data [15:0] Hold After ALE Deasserted ADAH t WR Pulse Width ALE Deasserted to Address/Data[15:0] In High Z ALEHZ t Address/Data [15:0] Setup Before WR High ...
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... Referenced to the sample edge. 2 Referenced to drive edge. Serial port signals (SCLK, FS, DxA,/DxB) are routed to the DAI_P[20:1] pins using the SRU. Therefore, the timing specifi- cations provided below are valid at the DAI_P[20:1] pins Rev Page May 2004 ADSP-21262 Min Max Unit 2.5 ns 2.5 ns 2 ...
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... ADSP-21262 Table 25. Serial Ports—Enable and Three-State Parameter Switching Characteristics t Data Enable from External Transmit SCLK DDTEN t Data Disable from External Transmit SCLK DDTTE t Data Enable from Internal Transmit SCLK DDTIN 1 Referenced to drive edge. Table 26. Serial Ports—External Late Frame Sync ...
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... DAI_P[20:1] (SCLK) t HFSI SFSI DAI_P[20:1] (FS) DAI_P[20:1] (DATA CHANNEL A/B) t DDTEN t DDTIN Figure 22. Serial Ports Rev Page May 2004 ADSP-21262 DATA RECEIVE— EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKW t DFSE t t SFSE HOFSE t SDRE DATA TRANSMIT — EXTERNAL CLOCK DRIVE EDGE ...
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... ADSP-21262 Input Data Port (IDP) The timing requirements for the IDP are given in Signals (SCLK, FS, SDATA) are routed to the DAI_P[20:1] pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P[20:1] pins. Table 27. Input Data Port Parameter Timing Requirements ...
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... DAI_P[4:1]. The timing below is valid at the DAI_P[20:1] pins or at the AD[15:0] pins. Min 1 2.5 1 2.5 1 2 × × t SAMPLE EDGE t PDCLK t PDCLKW t SPCLKEN t HPCLKEN t t PDSD PDHD t PDSTRB t PDHLDD Figure 24. PDAP Timing Rev Page May 2004 ADSP-21262 Max Unit CCLK – CCLK ...
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... ADSP-21262 SPI Interface—Master Table 29. SPI Interface Protocol — Master Switching and Timing Specifications Parameter Switching Characteristics t Serial Clock Cycle SPICLKM t Serial Clock High Period SPICHM t Serial Clock Low Period SPICLM t SPICLK Edge to Data Out Valid (Data Out Delay Time) DDSPIDM ...
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... MSB (OUTPUT) CPHASE = 0 MOSI MSB VALID (INPUT MSB MSB VALID LSB VALID LSB LSB VALID Figure 26. SPI Slave Timing Rev Page May 2004 ADSP-21262 Min Max Unit 7 × t – CCLK 5 × CCLK 4 × CCLK 2 × t – CCLK 2 × t – CCLK 2 × t ...
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... ADSP-21262 JTAG Test Access Port and Emulation Table 31. JTAG Test Access Port and Emulation Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High SSYS ...
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... OUTPUT DRIVE CURRENTS Figure 28 shows typical I-V characteristics for the output driv- ers of the ADSP-21262. The curves represent the current drive capability of the output drivers as a function of output voltage 3.11V, 70° -10 3.3V, 25° C 3.11V, 70° -30 3.47V, 0° C -40 0 0.5 1 1.5 ...
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... LOAD CAPACITANCE (pF) Figure 33. Typical Output Delay or Hold vs. Load Capacitance (at Ambient Temperature) ENVIRONMENTAL CONDITIONS The ADSP-21262 processor is rated for performance over the commercial temperature range 0°C to 70°C. AMB THERMAL CHARACTERISTICS Table 32 and Table 33 airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6 and the junction-to- board measurement complies with JESD51-8 ...
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... BGA PIN CONFIGURATIONS The following table and shows the ADSP-21262’s pin names and their default function after reset (in parentheses). on Page 41 shows the BGA package pin assignments. Table 34. 136-Ball BGA Pin Assignments Pin Name BGA Pin Pin Name No. CLKCFG0 A01 ...
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... ADSP-21262 Table 34. 136-Ball BGA Pin Assignments (Continued) Pin Name BGA Pin Pin Name No. AD5 J01 AD3 AD4 J02 V DDINT GND J04 GND GND J05 GND GND J06 GND GND J09 GND GND J10 GND GND J11 GND V J13 GND DDINT DAI_P16 (SD4B) ...
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... KEY V A GND* DDINT VDD V A I/O SIGNALS DDEXT VSS *USE THE CENTER BLOCK OF GROUND PINS TO PROVIDE THERMAL PATHWAYS TO YOUR PRINTED CIRCUIT BOARD’S GROUND PLANE. Figure 34. 136-Ball BGA Pin Assignments (Bottom View, Summary) Rev Page May 2004 ADSP-21262 ...
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... ADSP-21262 144-LEAD LQFP PIN CONFIGURATIONS The following table shows the ADSP-21262’s pin names and their default function after reset (in parentheses). Table 35. 144-Lead LQFP Pin Assignments Pin Name LQFP Pin Name Pin No DDINT DDINT CLKCFG0 2 GND CLKCFG1 3 RD BOOTCFG0 4 ALE BOOTCFG1 ...
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... PACKAGE DIMENSIONS The ADSP-21262 is available in a 136-ball BGA package and a 144-lead LQFP package shown in Figure 35 12.00 BSC SQ PIN A1 INDICATOR TOP VIEW 1.70 MAX 1. DIMENSIONS ARE IN MILIMETERS (MM). 2. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.150 MM OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. ...
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... Range ADSP-21262SKBC-200 + ADSP-21262SKBCZ200 + ADSP-21262SKSTZ200 + indicates Ball Grid Array package. ST indicates Low Profile Quad Flat package Pb-free part. For more information about lead-free package offerings, please visit www.analog.com. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. ...