DS2151Q Maxim Integrated Products, DS2151Q Datasheet
DS2151Q
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DS2151Q Summary of contents
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... PIN CONFIGURATION R Formats Dallas DS2151Q T1SCT ALE(AS) WR (R/W) RLINK RLCLK DVSS RCLK RCHCLK RSER RSYNC RLOS/LOTC SYSCLK PIN- PACKAGE 44 PLCC 44 PLCC DS2151Q FUNCTIONAL BLOCKS PARALLEL CONTROL PORT ACTUAL SIZE OF 44-PIN PLCC TSER 7 39 TCLK 8 38 DVDD 9 37 DS2151Q TSYNC 10 36 TLINK ...
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... DETAILED DESCRIPTION....................................................................................................4 1.1 I ................................................................................................................................ 4 NTRODUCTION 2 PIN DESCRIPTION................................................................................................................6 2.1 DS2151Q R M EGISTER 3 PARALLEL PORT .................................................................................................................9 4 CONTROL REGISTERS......................................................................................................10 4 ......................................................................................................................... 15 OCAL OOPBACK 4 ...................................................................................................................... 15 EMOTE OOPBACK 4 ..................................................................................................................... 15 AYLOAD OOPBACK 4 ...................................................................................................................... 15 RAMER OOPBACK 4 OOP ODE ENERATION 4 ULSE ENSITY NFORCER 4 OWER P EQUENCE 5 STATUS AND INFORMATION REGISTERS ......................................................................19 5.1 ...
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... Figure 1-1. DS2151Q Block Diagram ......................................................................................................... 5 Figure 13-1. External Analog Connections............................................................................................... 43 Figure 13-2. Jitter Tolerance .................................................................................................................... 43 Figure 13-3. Transmit Waveform Template .............................................................................................. 44 Figure 13-4. Jitter Attenuation .................................................................................................................. 45 Figure 14-1. Receive Side D4 Timing....................................................................................................... 46 Figure 14-2. Receive Side ESF Timing .................................................................................................... 46 Figure 14-3. Receive Side Boundary Timing with Elastic Store(s) Disabled ............................................ 47 Figure 14-4 ...
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... The analog AMI waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of the DS2151Q. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing pattern ...
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... Figure 1-1. DS2151Q Block Diagram ...
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PIN DESCRIPTION PIN NAME TYPE 1–4, AD4–AD7, I/O 41–44 AD0–AD3 5 RD(DS ALE(AS) I WR(R/ RLINK O 10 RLCLK O 11 DVSS — 12 RCLK O 13 RCHCLK O 14 RSER ...
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... Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries for the DS2151Q. Via TCR2.2, the DS2151Q can be programmed to output either a frame or multiframe pulse at this pin. If this pin is set to output pulses at frame boundaries, it can also be set via TCR2.4 to output double-wide pulses at signaling frames ...
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... DS2151Q Register Map ADDRESS R/W REGISTER NAME 20 R/W Status Register 1 21 R/W Status Register 2 22 R/W Receive Information Register 1 Line Code Violation Count 23 R Register 1 Line Code Violation Count 24 R Register 2 Path Code Violation Count 25 R Register 1 (Note 1) Path Code Violation Count ...
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... Addresses must be valid prior to the falling edge of ALE (AS), at which time the DS2151Q latches the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later portion of the DS or pulses ...
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... The operation of the DS2151Q is configured via a set of eight registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2151Q has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. There ...
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RCR2: RECEIVE CONTROL REGISTER 2 (Address = 2C Hex) (MSB) RCS RZBTSI SYMBOL POSITION RCS RCR2.7 RZBTSI RCR2.6 RSDW RCR2.5 RSM RCR2.4 RSIO RCR2.3 RD4YM RCR2.2 FSBE RCR2.1 MOSCRF RCR2.0 RSDW RSM RSIO NAME AND DESCRIPTION Receive Code Select. 0 ...
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... TCR1.3 TLINK TCR1.2 TBL TCR1.1 TYEL TCR1.0 Note: For a detailed description of how the bits in TCR1 affect the transmit side formatter of the DS2151Q, see Figure 14-9. TCPT RBSE GB7S NAME AND DESCRIPTION Loss Of Transmit Clock Mux Control. Determines whether the transmit side formatter should switch to the ever present ...
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TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 36 Hex) (MSB) TEST1 TEST0 SYMBOL POSITION TEST1 TCR2.7 TEST0 TCR2.6 TZBTSI TCR2.5 TSDW TCR2.4 TSM TCR2.3 TSIO TCR2.2 TD4YM TCR2.1 B7ZS XTCR2.0 Table 4-1. Output Pin Test Modes TEST1 TEST0 0 0 ...
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CCR1: COMMON CONTROL REGISTER 1 (Address = 37 Hex) (MSB) TESE LLB SYMBOL POSITION TESE CCR1.7 LLB CCR1.6 RSAO CCR1.5 RLB CCR1.4 SCLKM CCR1.3 RESE CCR1.2 PLB CCR1.1 FLB CCR1.0 RSAO RLB SCLKM NAME AND DESCRIPTION Transmit Elastic Store Enable. ...
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... BPVs that might have occurred intact) via the TTIP and TRING pins. Data will continue to pass through the receive side of the DS2151Q as it would normally and the data at the TSER input will be ignored. Data in this loopback will pass through the jitter attenuator. RLB is used to place the DS2151Q into “ ...
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CCR2: COMMON CONTROL REGISTER 2 (Address = 38 Hex) (MSB) TFM TB8ZS SYMBOL POSITION TFM CCR2.7 TB8ZS CCR2.6 TSLC96 CCR2.5 TFDL CCR2.4 RFM CCR2.3 RB8ZS CCR2.2 RSLC96 CCR2.1 RFDL CCR2.0 TSLC96 TFDL RFM NAME AND DESCRIPTION Transmit Frame Mode Select. ...
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CCR3: COMMON CONTROL REGISTER 3 (Address = 30 Hex) (MSB) ESMDM ESR SYMBOL POSITION ESMDM CCR3.7 ESR CCR3.6 P16F CCR3.5 RSMS CCR3.4 PDE CCR3.3 TLD CCR3.2 TLU CCR3.1 LIRST CCR3.0 P16F RSMS PDE NAME AND DESCRIPTION Elastic Store Minimum Delay ...
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... Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits respectively. When the CCR3.3 is set to 1, the DS2151Q will force the transmitted stream to meet this requirement no matter the content of the transmitted stream. When running B8ZS, the CCR3.3 bit should be set to 0, since B8ZS encoded data streams cannot violate the pulse density requirements ...
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... The user will always precede a read of these registers with a write. The byte written to the register will inform the DS2151Q which bits the user wishes to read and have cleared. The user will write a byte to one of these four registers, with the bit positions he or she wishes to read and the bit positions he or she does not wish to obtain the latest information on ...
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RIR1: RECEIVE INFORMATION REGISTER 1 (Address = 22 Hex) (MSB) COFA 8ZD SYMBOL POSITION COFA RIR1.7 8ZD RIR1.6 16ZD RIR1.5 RESF RIR1.4 RESE RIR1.3 SEFE RIR1.2 B8ZS RIR1.1 FBE RIR1.0 16ZD RESF RESE NAME AND DESCRIPTION Change of Frame Alignment. ...
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RIR2: RECEIVE INFORMATION REGISTER 2 (Address = 31 Hex) (MSB) RL1 RL0 SYMBOL POSITION RL1 RIR2.7 RL0 RIR2.6 TESF RIR2.5 TESE RIR2.4 TSLIP RIR2.3 JALT RIR2.2 RPDV RIR2.1 TPDV RIR2.0 Table 5-1. Receive T1 Level Indication TYPICAL LEVEL RL1 RL0 ...
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SR1: STATUS REGISTER 1 (Address = 20 Hex) (MSB) LUP LDN SYMBOL POSITION LUP SR1.7 LDN SR1.6 LOTC SR1.5 RSLIP SR1.4 RBL SR1.3 RYEL SR1.2 RCL SR1.1 RLOS SR1.0 LOTC RSLIP RBL NAME AND DESCRIPTION Loop Up Code Detected. Set ...
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... The blue alarm criteria in the DS2151Q has been set to achieve this performance recommended that the RBL bit be qualified with the RLOS status bit in detecting a blue alarm. ...
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SR2: STATUS REGISTER 2 (Address = 21 Hex) (MSB) RMF TMF SYMBOL POSITION RMF SR2.7 TMF SR2.6 SEC SR2.5 RFDL SR2.4 TFDL SR2.3 RMTCH SR2.2 RAF SR2.1 — SR2.0 SEC RFDL TFDL NAME AND DESCRIPTION Receive Multiframe. Set on receive ...
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IMR1: INTERRUPT MASK REGISTER 1 (Address = 7F Hex) (MSB) LUP LDN SYMBOL POSITION LUP IMR1.7 LDN IMR1.6 LOTC IMR1.5 SLIP IMR1.4 RBL IMR1.3 RYEL IMR1.2 RCL IMR1.1 RLOS IMR1.0 LOTC SLIP RBL NAME AND DESCRIPTION Loop Up Code Detected. ...
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IMR2: INTERRUPT MASK REGISTER 2 (Address = 6F Hex) (MSB) RMF TMF SYMBOL POSITION RMF TMF SEC RFDL TFDL RMTCH RAF — SEC RFDL TFDL NAME AND DESCRIPTION IMR2.7 Receive Multiframe interrupt masked 1 = interrupt enabled IMR2.6 ...
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... ERROR COUNT REGISTERS There are a set of three counters in the DS2151Q that record bipolar violations, excessive 0s, errors in the CRC6 codewords, framing bit errors, and number of multiframes that the device is out of receive synchronization. Each of these three counters are automatically updated on one second boundaries as determined by the one second timer in Status Register 2 (SR2 ...
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... Path Code Violation Count Register (PCVCR) When the receive side of the DS2151Q is set to operate in the ESF framing mode (CCR2.3 = 1), PCVCR will automatically be set as a 12-bit counter that will record errors in the CRC6 codewords. When set to operate in the D4 framing mode (CCR2.3 = 0), PCVCR will automatically count errors in the Ft framing bit position ...
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Multiframes Out of Sync Count Register (MOSCR) Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of sync (RCR2.0 = 1). This number is useful in ESF applications needing to measure ...
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... If the 0 destuffer sees six or more row followed the 0 is not removed. The CCR2.0 bit should always be set when the DS2151Q is extracting the FDL. More on how to use the DS2151Q in FDL and SLC-96 applications is covered in a separate application note. Also, contact the factory for C code software that implements both ANSI T1.403 and AT& ...
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... If it finds such a pattern, it will automatically insert a 0 after the five 1s. The CCR2.4 bit should always be set when the DS2151Q is inserting the FDL. More on how to use the DS2151Q in FDL and SLC-96 applications is covered in a separate application note. ...
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... The Robbed-Bit signaling bits embedded in the T1 stream can be extracted from the receive stream and inserted into the transmit stream by the DS2151Q. There is a set of 12 registers for the receive side (RS1 to RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below. ...
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... TSRs. In the D4 framing mode, there are only 2 framing bits per channel (A and B). However in the D4 framing mode, the DS2151Q uses the C and D bit positions as the A and B bit positions for the next multiframe. The DS2151Q will load the values in the TSRs into the outgoing shift register every other D4 multiframe ...
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... TRANSMIT TRANSPARENCY AND IDLE REGISTERS There is a set of seven registers in the DS2151Q that can be used to custom tailor the data that transmitted onto the T1 line channel-by-channel basis. Each of the 24 T1 channels can be either forced to be transparent or to have a user defined idle code inserted into them. Each of these special registers is defined below ...
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TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 3F Hex) (MSB) TIDR7 TIDR6 SYMBOL POSITION TIDR7 TIDR0 Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in the outgoing frame. When these bits are set ...
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CLOCK BLOCKING REGISTERS The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either high or low ...
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... RCLK and all of the slip contention logic in the DS2151Q is disabled (since slips cannot occur). Also, since the buffer depth is no longer two frames deep, the DS2151Q must be set up to source either a frame or multiframe pulse at the RSYNC pin. On power-up after the SYSCLK has locked to the RCLK signal, the Elastic Store Reset bit (CCR3 ...
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... RECEIVE MARK REGISTERS The DS2151Q can replace the incoming data on a channel-by-channel basis with either an idle code (7F hex) or the digital milliwatt code, which is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). The RCR2.7 bit will determine which code is used. Each bit in the RMRs, represents a particular channel ...
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... LINE INTERFACE FUNCTIONS The line interface function in the DS2151Q contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the T1 line; and the jitter attenuator. Each of these three sections is controlled by the Line Interface Control Register (LICR), which is described below ...
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... EGL bit should be set some applications, more sensitivity than -30dB may be required and the DS2151Q will allow the receiver low as -36dB if the EGL bit is set to 0. However, when the EGL bit is set to 0, the DS2151Q will be more susceptible to crosstalk and its jitter tolerance will suffer ...
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... Due to the nature of the design of the transmitter in the DS2151Q, very little jitter (less than 0.005UI broadband from 10Hz to 100kHz) is added to the jitter present on TCLK. Also, the waveforms that they create are independent of the duty cycle of TCLK. The transmitter in the DS2151Q couples to the T1 transmit twisted pair via a 1:1 ...
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... Jitter Attenuator The DS2151Q contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via the JABDS bit in the Line Interface Control Register (LICR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. ...
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Figure 13-1. External Analog Connections NOTE: SEE THE SEPARATE APPLICATION NOTE FOR DETAILS ON HOW TO CONSTRUCT A PROTECTED INTERFACE. Figure 13-2. Jitter Tolerance ...
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Figure 13-3. Transmit Waveform Template ...
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Figure 13-4. Jitter Attenuation ...
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TIMING DIAGRAMS Figure 14-1. Receive Side D4 Timing NOTE 1: RSYNC IN THE FRAME MODE (RCR2 AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RCR2.5 = 0). NOTE 2: RSYNC IN THE FRAME MODE (RCR2 AND ...
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Figure 14-3. Receive Side Boundary Timing with Elastic Store(s) Disabled NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. NOTE 2: AN ESF BOUNDARY IS SHOWN. Figure 14-4. 1.544MHz Boundary Timing with Elastic Store(s) Enabled NOTE 1: RSYNC IS IN ...
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Figure 14-5. 2.048MHz Boundary Timing with Elastic Store(s) Enabled NOTE 1: RSER DATA IN CHANNELS 13, 17, 21, 25, AND 29 ARE FORCED TO 1; TSER IGNORED DURING THESE CHANNELS. NOTE 2: RSYNC IS IN THE OUTPUT ...
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Figure 14-7. Transmit Side ESF Timing NOTE 1: TSYNC IN THE FRAME MODE (TCR2 AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TCR2.4 = 0). NOTE 2: TSYNC IN THE FRAME MODE (TCR2 AND DOUBLE-WIDE FRAME SYNC ...
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Figure 14-8. Transmit Side Boundary Timing with Elastic Store(s) Disabled NOTE 1: TSYNC IS IN THE INPUT MODE (TCR2.2 = 0). NOTE 2: TSYNC IS IN THE OUTPUT MODE (TCR2.2 = 1). NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL ...
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Figure 14-9. Transmit Data Flow ...
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... This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Table 15-1. Recommended DC Characteristics (T = 0°C to +70°C for DS2151Q PARAMETER Logic 1 Logic 0 Supply Table 15-2 ...
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... AC CHARACTERISTICS Table 16-1. AC Characteristics—Parallel Port = 5V ±5 0°C to +70°C for DS2151Q (See Figure 16-1, Figure 16-2, and PARAMETER Cycle Time Pulse Width, DS Low or RD High Pulse Width, DS High or RD Low Input Rise/Fall Times R/ Hold Time W R/ Setup Time before DS ...
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Figure 16-1. Intel Bus Read AC Timing Figure 16-2. Intel Bus Write AC Timing ...
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Figure 16-3. Motorola Bus AC Timing ...
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... Table 16-2. AC Characteristics—Receive Side = 5V ±5 0°C to +70°C for DS2151Q (See Figure 16-4.) PARAMETER ACLKI/RCLK Period RCLK Pulse Width RCLK Pulse Width SYSCLK Period SYSCLK Pulse Width RSYNC Setup to SYSCLK Falling RSYNC Pulse Width SYSCLK Rise/Fall Times Delay RCLK or SYSCLK to ...
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Figure 16-4. Receive Side AC Timing NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR2.3 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR2.3 = 1). NOTE 3: RLCLK AND RLINK ONLY HAVE A TIMING RELATIONSHIP TO RCLK. ...
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... Table 16-3. AC Characteristics—Transmit Side = 5V ±5 0°C to +70°C for DS2151Q (See Figure 16-5.) PARAMETER TCLK Period TCLK Pulse Width TSER and TLINK Set up to TCLK Falling TSER and TLINK Hold from TCLK Falling TSYNC Set up to TCLK Falling TSYNC Pulse Width ...
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Figure 16-5. Transmit Side AC Timing NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR2.2 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR2.2 = 0). NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF SYSCLK IF ...
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... No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor © 2006 Maxim Integrated Products • Printed USA DS2151Q ...