AM79C970KC Advanced Micro Devices, AM79C970KC Datasheet
AM79C970KC
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AM79C970KC Summary of contents
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... This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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PCnet Family, including the PCnet-ISA controller (Am79C960), the PCnet-ISA (Am79C961), and the PCnet-32 (Am79C965). The buffer management unit supports the LANCE, ILACC, and PCnet descriptor software models. The PCnet-PCI controller is software compatible with the Novell NE2100 ...
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AMD DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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MENDEC Transmit Path . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD USER ACCESSIBLE REGISTERS PCI Configuration Registers Vendor ...
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CSR38: Next Transmit Descriptor Address Lower CSR39: Next Transmit Descriptor Address Upper CSR40: Current Receive Status and Byte Count Lower CSR41: Current Receive Status and Byte Count Upper CSR42: ...
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AMD Bus Configuration Registers BCR0: Master Mode Read Active BCR1: Master Mode Write Active BCR2: Miscellaneous Configuration BCR4: Link Status LED (LNKST) BCR5: LED1 Status BCR6: LED2 Status BCR7: LED3 Status BCR16: I/O Base Address Lower BCR17: I/O Base Address ...
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ABSOLUTE MAXIMUM RATINGS OPERATING RANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD RELATED PRODUCTS Part No. Description Am79C98 Twisted-Pair Ethernet Transceiver (TPEX) Am79C100 Twisted-Pair Ethernet Transceiver Plus (TPEX+) Am7996 IEEE 802.3/Ethernet/Cheapernet Tap Transceiver Am79C981 Integrated Multiport Repeater Plus Am79C987 Hardware Implemented Management Information Base Am79C940 Media Access Controller for Ethernet (MACE ...
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CONNECTION DIAGRAM VDD 1 AD27 2 AD26 3 VSSB 4 AD25 5 AD24 6 C/BE3 7 VDD 8 9 RESERVED IDSEL 10 VSS 11 AD23 12 AD22 13 VSSB 14 AD21 15 AD20 16 VDDB 17 AD19 18 AD18 19 ...
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AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C970 K DEVICE NUMBER/DESCRIPTION Am79C970 PCnet-PCI Single-Chip Ethernet Controller for PCI Local Bus ...
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PIN DESIGNATIONS Listed by Pin Number Pin No. Pin Name Pin No. 1 VDDB 2 AD27 3 AD26 4 VSSB 5 AD25 6 AD24 7 C/BE3 8 VDD 9 RESERVED 10 IDSEL 11 VSS 12 AD23 13 AD22 14 VSSB ...
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AMD PIN DESIGNATIONS Listed by Group Pin Name Pin Function PCI Bus Interface AD[31:00] Address/Data Bus C/BE[3:0] Bus Command/Byte Enable CLK Bus Clock DEVSEL Device Select FRAME Cycle Frame GNT Bus Grant IDSEL Initialization Device Select INTA Interrupt IRDY Initiator ...
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PIN DESIGNATIONS Listed by Driver Type The next table describes the various types of drivers that are implemented in the PCnet-PCI controller. Current is given as milliamperes: Name Type TM TS3 Tri-State TS6 Tri-State O3 Totem Pole O8 Totem Pole ...
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AMD PIN DESCRIPTION PCI Interface AD[31:00] Address and Data Input/Output These signals are multiplexed on the same PCI pins. During the first clock of a transaction AD[31:00] contain the physical byte address (32 bits). During the subse- quent clocks AD[31:00] ...
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INTA Interrupt Request Input/Output An asynchronous attention signal which indicates that one or more of the following status flags is set: BABL, MISS, MERR, RINT, IDON, RCVCCO, RPCO, JAB, MPCO, or TXSTRT. Each status flag has a mask bit which ...
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AMD When RST is active, NAND tree testing is enabled. All PCI interface pins are in input mode. The result of the NAND tree testing can be observed on the NOUT output (pin 62). SERR System Error Input/Output This signal ...
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SLEEP. All I/O accesses to the PCnet-PCI controller will result in a PCI target abort response. The PCnet-PCI controller will not assert REQ while in sleep mode. When SLEEP is as- serted, all non-PCI ...
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AMD Attachment Unit Interface CI Collision In Input A differential input pair signaling the PCnet-PCI control- ler that a collision has been detected on the network me- dia, indicated by the CI inputs being driven with a 10 MHz pattern ...
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BASIC FUNCTIONS System Bus Interface Function The PCnet-PCI controller is designed to operate as a Bus Master during normal operations. Some slave I/O accesses to the PCnet-PCI controller are required in normal operations as well. Initialization of the PCnet- PCI ...
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AMD DETAILED FUNCTIONS Bus Interface Unit (BIU) The bus interface unit is built of several state machines that run synchronously to CLK. One bus interface unit state machine handles accesses where the PCnet-PCI controller is the bus slave, and another ...
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Bus Master DMA Transfers There are four primary types of DMA transfers. The PCnet-PCI controller uses non-burst as well as burst cy- cles for read and write access to the main memory. Basic Non-Burst Read Cycles The PCnet-PCI controller uses ...
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AMD Figure 3 shows two non-burst read access within one ar- bitration cycle. The PCnet-PCI controller will drop FRAME between two consecutive non-burst read cy- cles. The PCnet-PCI controller will re-request the bus right again preempted before ...
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Basic Burst Read Cycles The PCnet-PCI controller provides a burst mode to read data from the transmit buffer. The burst mode must be enabled by setting BREADE in BCR18. All PCnet-PCI controller burst read transfers are of the PCI command ...
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AMD Basic Non-Burst Write The PCnet-PCI controller uses non-burst write cycles to access the receive and transmit descriptor entries. Some of the write accesses to the receive buffer mem- ory are also in non-burst mode. All PCnet-PCI controller non-burst write ...
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Basic Burst Write Cycles The PCnet-PCI controller provides a burst mode to write data to the receive buffer. The burst mode must be en- abled by setting BWRITE in BCR18. All PCnet-PCI con- troller burst write transfers are of the ...
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AMD Target Initiated Termination When the PCnet-PCI controller is a bus master, the cy- cles it produces on the PCI bus may be terminated by the target in one of three different ways. Disconnect With Data Transfer Figure 7 shows ...
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Disconnect Without Data Transfer Figure 8 shows a target disconnect sequence during which no data is transferred. STOP is asserted on clock 4 without TRDY being asserted at the same time. The PCnet-PCI controller terminates the current transfer with the ...
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AMD Target Abort Figure 9 shows a target abort sequence. The target as- serts DEVSEL for one clock. It then deasserts DEVSEL and asserts STOP on clock 4. A target can use the target abort sequence to indicate that it ...
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Master Initiated Termination There are three scenarios besides normal completion of a transaction where the PCnet-PCI controller will termi- nate the cycles it produces on the PCI bus. Preemption When FRAME is Deasserted The PCnet-PCI controller will generate multiple address ...
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AMD Preemption When FRAME is Asserted The central arbiter can take GNT to the PCnet-PCI con- troller away if the current bus operation takes too long. This may happen e.g. when the PCnet-PCI controller tries to fill the whole transmit ...
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Master Abort The PCnet-PCI controller will terminate its cycle with a Master Abort sequence if DEVSEL is not asserted within 4 clocks after FRAME is asserted. Master Abort is treated as a fatal error by the PCnet-PCI controller. The PCnet-PCI ...
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AMD Initialization Block DMA Transfers During execution of the PCnet-PCI controller bus mas- ter initialization procedure, the PCnet-PCI microcode will repeatedly request DMA transfers from the BIU. During each of these initialization block DMA transfers, the BIU will perform two ...
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Descriptor DMA Transfers PCnet-PCI microcode will determine when a descriptor access is required. A descriptor DMA read will consist of two DWORD (double-word) transfers. A descriptor DMA write will consist of one or two DWORD transfers. (The transfers within a ...
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AMD CLK 1 2 FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled by the PCnet-PCI controller. * Note that Message Descriptor addresses 1 and 0 are in descending order. 1-902 ...
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CLK FRAME AD C/BE PAR IRDY TRDY DEVSEL REQ GNT DEVSEL is sampled by the PCnet-PCI controller. * Note that Message Descriptor addresses 2 and 1 ...
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AMD FIFO DMA Transfers PCnet-PCI microcode will determine when a FIFO DMA transfer is required. This transfer mode will be used for transfers of data to and from the PCnet-PCI FIFOs. Once the PCnet-PCI BIU has been granted bus maste- ...
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If DMAPLUS = 0, a maximum of 16 transfers will be performed by default. This default value may be changed by writing to the DMA Transfer Counter (CSR80). Note that DMAPLUS = 0 merely sets a maximum value. The minimum ...
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AMD It is not necessary for the software to insure that the buffer address pointer contained in descriptor word 0 matches the address restrictions given in the table. If the buffer pointer does not meet the conditions set forth in ...
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Partial Linear Burst Certain factors may cause the PCnet-PCI controller to burst fewer than the LINBC limit during a single burst se- quence. Factors that could generate a partial linear burst include: No more data available for transfers from the ...
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AMD Figure 17 shows a partial linear burst that occurred while approaching the transfer of the last bytes of data buffer. The linear burst begins when 10 bytes of space still remain in the RX buffer. (The ...
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Slave I/O Transfers After the PCnet-PCI controller is configured as I/O de- vice (by setting IOEN in the PCI Command register), it starts monitoring the PCI bus for access to its internal registers. The PCnet-PCI controller will look for an ...
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AMD Slave I/O Write The Slave I/O Write command is used by the host CPU to write to the PCnet-PCI’s CSRs, BCRs and EEPROM locations single cycle, non-burst 16-bit or 32-bit transfer which is initiated by the ...
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Slave Configuration Transfers The host can access the PCnet-PCI PCI configuration space with a configuration read or write command. The PCnet-PCI controller will assert DEVSEL if the IDSEL input is asserted during the address phase and if the ac- cess ...
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AMD Slave Configuration Write The Slave Configuration Write command is used by the host CPU to write the configuration space in the PCnet- PCI controller. This allows the host CPU to control basic CLK FRAME AD C/BE PAR IRDY TRDY ...
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Buffer Management Unit (BMU) The buffer management unit is a micro-coded state ma- chine which implements the initialization procedure and manages the descriptors and buffers. The buffer man- agement unit operates at half the speed of the CLK input. Initialization ...
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AMD entry. A device may, however, read from a descriptor that it does not currently own. Software should always read descriptor entries in sequential order. When soft- ware finds that the current descriptor is owned by the PCnet-PCI controller, then ...
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When SSIZE32 = 1, software data structures are 32 bits wide. The following diagram illustrates, Figure 23, the relationship between the Initialization Base Address, the Initialization Block, the Receive and Transmit 32-Bit Base Address Pointer to Initialization Block CSR2 CSR1 ...
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AMD Polling If there is no network channel activity and there is no pre- or post-receive or pre- or post-transmit activity be- ing performed by the PCnet-PCI controller, then the PCnet-PCI controller will periodically poll the current re- ceive and ...
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If the OWN bit is set and the buffer length is 0, the OWN bit will be reset. In the LANCE the buffer length interpreted as a 4096-byte buffer acceptable to have a 0 length ...
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AMD Receive Descriptor Table Entry (RDTE) If the PCnet-PCI controller does not own both the cur- rent and the next Receive Descriptor Table Entry then the PCnet-PCI controller will continue to poll according to the polling sequence described above. If ...
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Both features can be independ- ently over-ridden ...
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AMD The status of each receive message is available in the appropriate RMD and CSR areas. FCS and Framing er- rors (FRAM) are reported, although the received frame is still passed to the host. The FRAM error will only be ...
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This transmit two part deferral algorithm is implemented as an option which can be disabled using the DXMT2PD bit in CSR3. Two part deferral after transmission is use- ful for ...
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AMD Manchester Encoder/Decoder (MENDEC) The integrated Manchester Encoder/Decoder provides the PLS (Physical Layer Signaling) functions required for a fully compliant ISO 8802-3 (IEEE/ANSI 802.3) sta- tion. The MENDEC provides the encoding function for data to be transmitted on the network ...
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Transmission is enabled by the controller. As long as the ITXEN request remains active, the serial output of the controller will be Manchester encoded and appear When the internal request is dropped by the con- troller, the ...
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AMD difference between BCC and phase-locked clock. Hence, input data jitter is reduced in ISRDCLK Carrier Tracking and End of Message The carrier detection circuit monitors the DI inputs after IRXCRS is asserted for an end ...
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Collision Detection A MAU detects the collision condition on the network and generates a differential signal at the CI inputs. This collision signal passes through an input stage which de- tects signal levels and pulse duration. When the signal is ...
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AMD inactivity, ’Link beat pulses’ will be periodically sent over the twisted pair medium to constantly monitor me- dium integrity. When the link test function is enabled (DLNKTST bit in CSR15 is cleared), the absence of link beat pulses and ...
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Collision Detect Function Activity on both twisted pair signals RXD and TXD constitutes a collision, thereby causing the COL signal to be activated. (COL is used by the LED control circuits) COL will remain active until one of the two ...
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AMD Power Savings Modes The PCnet-PCI controller supports two hardware power savings modes. Both are entered by driving the SLEEP pin LOW. The PCI interface section is not effected by SLEEP. In particular, access to the PCI configuration space re- ...
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Device ID Status Base-Class Reserved Reserved The configuration registers are accessible only by PCI configuration cycles. They can be accessed right after the PCnet-PCI controller is powered-on, even if the read operation of the serial EEPROM is ...
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AMD Software may invoke DWIO mode by performing a Dou- ble Word write access to the I/O location at offset 10h (RDP). Note that even though the I/O resource mapping changes when the I/O mode setting changes, the RDP location ...
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The Vendor Specific Word (VSW) is not implemented by the PCnet-PCI controller. This particular I/O address is reserved for customer use and will not be used by future AMD Ethernet controller products. DWIO I/O Resource Map When the PCnet-PCI controller ...
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AMD APROM Access The APROM space is a convenient place to store the value of the 48-bit IEEE station address. This space is automatically loaded from the serial EEPROM EEPROM is present. It can be overwritten by the ...
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If DWIO mode has been invoked, then the BDP has a width of 32 bits, hence, all BCR ...
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AMD Table 6 describes all possible bus master accesses that the PCnet-PCI controller will perform. The right most Access Mode 4-byte read Read 4-byte write Write 3-byte write Write 3-byte write Write 2-byte write Write 2-byte write Write 2-byte write ...
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Table 7 describes all possible bus slave accesses that may be directed toward the PCnet-PCI controller. (i.e., the PCnet-PCI controller is the target device during the transfer.) The first column indicates the type of slave ac- cess. RD stands for ...
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AMD H_RESET default values. The content of the APROM locations (offsets 0h – Fh from the I/O base address), however, will not be cleared. The 8-bit checksum for the entire 36 bytes of the EEPROM should be FFh ...
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Note that accesses to the APROM I/O locations do not directly access the Address EEPROM itself. Instead, these accesses are routed to a set of shadow registers on board the PCnet-PCI controller that are loaded with a copy of the ...
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AMD Transmit Operation The transmit operation and features of the PCnet-PCI controller are controlled by programmable options. The PCnet-PCI controller offers a136-byte Transmit FIFO to provide frame buffering for increased system latency, automatic retransmission with no FIFO reload, and automatic ...
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The 544 bit count is derived from the following: Minimum frame size (excluding preamble, including FCS) 64 bytes Preamble/SFD size 8 bytes FCS size 4 bytes To be classed as a minimum size frame at the receiver, the transmitted frame ...
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AMD goes inactive (this does not apply if the 10BASE-T port is selected). If the CI input is not asserted within the 40 network bit time period following the completion of transmission, then the PCnet-PCI controller will set the CERR ...
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Note that for some network protocols, the value passed in the Ethernet Type and/or 802.3 Length field is not compliant with either standard and may cause problems Bits Bits Preamble Sync Destination 1010....1010 10101011 Address Start of Frame ...
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AMD back mode, data can be transmitted to and received from the external network. There are restrictions on loopback operation. The PCnet-PCI controller has only one FCS generator cir- cuit. The FCS generator can be used by the transmitter to ...
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LED Default Default output Interpretation Drive Enable Output Polarity LNKST Link Status Enabled LED1 Receive Enabled LED3 Transmit Enabled For each LED register, each of the status signals is ANDed with its enable signal, and these signals are all ORed ...
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AMD NAND Tree Testing The PCnet-PCI controller provides a NAND tree test mode to allow checking connectivity to the device on a printed circuit board. The NAND tree is built on all PCI bus signals. VDD RST (pin 120) INTA ...
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Pin 120 (RST) is the first input to the NAND tree. Pin 117 (INTA) is the second input to the NAND tree, followed by pin 121 (CLK). All other PCI bus signals follow, counter- clockwise, with pin 57 (AD0) being ...
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AMD RST INTA CLK GNT REQ AD[31:0] FFFFFFFF C/BE[3:0] F IDSEL FRAME IRDY TRDY DEVSEL STOP LOCK PERR SERR PAR NOUT 1-946 0000FFFF 3 7 Figure 31. NAND Tree ...
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USER ACCESSIBLE REGISTERS The PCnet-PCI controller has three types of user regis- ters: the PCI configuration registers, the Control and Status registers (CSR) and the Bus Control registers (BCR). The PCnet-PCI controller implements all PCnet-ISA (Am79C960) registers all LANCE (Am7990) ...
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AMD CSR122 Receiver Packet Alignment Control BCR2 Misc. configuration BCR18 Bus Size and Burst Control Register BCR20 Software Style Running Registers The following is a list of those registers that would typi- cally need to be periodically read and perhaps ...
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Command Register (offset 04h) The Command register is a 16-bit register used to con- trol the gross functionality of the PCnet-PCI controller. It controls the PCnet-PCI controller’s ability to generate and respond to PCI bus cycles. To logically disconnect the ...
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AMD and the PAR lines for a parity er- ror at the following times: In slave mode, during the address phase of any PCI bus command. In slave mode, during the data phase of all I/O and Configuration Write commands ...
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Revision ID Register (Offset 08h) The Revision ID register is an 8-bit register that specifies the PCnet-PCI controller revision number. The current value of this register is 00h. The Revision ID register is located at offset 08h in the PCI ...
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AMD 1 RES Reserved location. Read as ZERO, write operations have no effect. 0 IOSPACE I/O space indicator. Read as ONE, write operations have no effect. Indicating that this Base Address register describes an I/O base address. Interrupt Line Register ...
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BABL will be set if 1519 bytes or greater are transmitted. When BABL is set, INTA is as- serted if IENA = 1 and the mask bit BABLM in ...
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AMD completed. When IDON is set, PCnet-PCI controller has read the Initialization memory. When IDON is set, INTA is as- serted if IENA = 1 and the mask bit IDONM in CSR3 is clear. IDON is set by the Buffer ...
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INIT is set by writing a “1”. Writing a “0” has no effect. INIT is cleared by H_RESET, S_RESET or by setting the STOP bit. CSR1: IADR[15:0] Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and ...
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AMD or S_RESET and is not affected by STOP. 11 MERRM Memory Error Mask. If MERRM is set, the MERR bit in CSR0 will be masked and unable to set INTR flag in CSR0. Read/Write accessible always. MERRM is cleared ...
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The interrupt is generated when the “header” bytes have been written to the “header” memory area. Read/Write accessible always. The LAPPEN bit will be reset to ZERO by S_RESET and ...
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AMD the Runt Packet Accept (RPA) bit (CSR124, bit 3) may be changed only when ENTST is set to ONE. To enable RPA, the user must first write a ONE to the ENTST bit. Next, the user must first write ...
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Also cleared by H_RESET, S_RESET or by setting the STOP bit. Writing a 0 has no effect. When RCVCCO is set, INTA is asserted if IENA is ONE and the mask bit RCVCCOM is ...
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AMD the PCnet-PCI controller initial- zation routine. Read accessible only when STOP bit is set. Write operations have no effect and should not be performed. RLEN is only defined after initialization. These bits are unaffected by H_RESET, S_RE- SET or ...
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CSR14: Physical Address Register, PADR[47:32] Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 PADR[47:32] Physical Address PADR[47:32]. The content of this register is undefined until loaded from the initialization block after the INIT ...
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AMD AUI drivers rest when the AUI transmit port is idle. When TSEL = 0, DO+ and DO– yield “zero” differential to operate trans- former coupled loads (Ethernet 2 and 802.3). When TSEL = 1, the DO+ idles at a ...
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DTX = “0”, will set TXON bit (CSR0 bit 4) if STRT (CSR0 bit 1) is asserted. Read/write accessible only when STOP bit is set. 0 DRX Disable Receiver PCnet-PCI controller not access- ing ...
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AMD Read/write accessible only when STOP bit is set. These bits are unaffected S_RESET or STOP. CSR24: Base Address of Receive Ring Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 BADRL Contains ...
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CSR32: Next Transmit Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 NXDAL Contains the lower 16 bits of the next TDRE address pointer. Read/write accessible only when STOP bit is ...
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AMD 15–0 NNXDAU Contains the upper 16 bits of the next next transmit descriptor ad- dress pointer. Read/write accessible only when STOP bit is set. These bits are unaffected S_RESET or STOP. CSR40: Current Receive Byte Count Bit Name Description ...
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CSR46: Poll Time Counter Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 POLL Poll Time Counter. This counter is incremented by the PCnet-PCI controller microcode and is used to trigger the descriptor ring ...
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AMD Initialization Block and Transmit and Receive descriptor bit maps are affected. When cleared, this bit indicates that the PCnet-PCI controller utilizes (PCnet-ISA) software structures. Note: Regardless of the setting of SSIZE32, the Initialization Block must always begin on a ...
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CSR60: Previous Transmit Descriptor Address Lower Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 PXDAL Contains the lower 16 bits of the previous TDRE address pointer. PCnet-PCI controller has the ca- pability to ...
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AMD Read/write accessible only when STOP bit is set. These bits are unaffected S_RESET or STOP. CSR67: Next Transmit Status Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–8 NXST Next Transmit Status. This ...
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RCVFW[1:0] Receive FIFO RCVFW controls the point at which receive DMA is requested in relation to the number of re- ceived bytes in the receive FIFO. RCVFW specifies the number of bytes which must be present (once the frame ...
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AMD Combinations of watermark set- tings and LINBC (BCR18, bits 2–0) settings must obey the following relationship: watermark (in bytes) LINBC (in bytes) Combinations of watermark and LINBC settings that violate this rule may cause unexpected behavior. 7–0 DMATC[7:0] DMA ...
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As an example, if the linear burst size is 4 transfers, and the num- ber of wait states for the system memory is 2, and the CLK period is 30ns and the MAX time ...
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AMD Note that this code is not the same as the Device ID in the PCI configuration space. 11 – 1 Manufacturer ID. The 11-bit manufacturer code for AMD is 00000000001. This code is per the JEDEC Publication 106-A. Note ...
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This register is always readable and is cleared by H_RESET or S_RESET or STOP. A write to this register performs an increment when the ENTST bit in CSR4 is set. CSR114: Receive Collision Count Bit Name Description 31–16 RES Reserved ...
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AMD Bus Configuration Registers The Bus Configuration Registers (BCR) are used to pro- gram the configuration of the bus interface and other special features of the PCnet-PCI controller that are not related to the IEEE 8802-3 MAC functions. The BCRs ...
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BCR0: Master Mode Read Active Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15–0 MSRDA Reserved locations. After H_RE- SET, the value in this register will be 0005h. The settings of this register will ...
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AMD port when the PORTSEL bits of the Mode Register (CSR15) have selected 10BASE-T as the active port. When ASEL is set to a ZERO, then the selected network port will be determined by the settings of the PORTSEL bits ...
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A value of 0 disables the signal. A value of 1 enables the signal. 5 RCVME Receive Match status Enable. In- dicates receive activity on the network that has passed the ad- dress match function for this node. All address ...
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AMD each new occurrence of the en- abled function for this LED output. A value of 0 disables the signal. A value of 1 enables the signal. 6 LNKSTE Link Status Enable. Indicates the current link status on the Twisted ...
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LOW level whenever the OR of the enabled signals is true and the LED pin will be disabled and allowed to float high whenever the OR of the enabled signals is false. (i.e. the ...
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AMD 4–0 RES Reserved locations. Written as ZEROS, read as undefined. BCR17: I/O Base Address Upper Bit Name Description Note that all bits in this register are programmable through the EEPROM PREAD operation. 31–16 RES Reserved locations. Written as ZEROs ...
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BWRITE Burst Write Enable. When set, this bit enables Linear Bursting during memory write accesses, where Linear Bursting is defined to mean that only the first transfer in the current bus arbitration will contain an address phase. Sub- sequent ...
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AMD gives a default linear burst length of 4 transfers = 001b x 4. BCR19: EEPROM Control and Status Register Bit Name Description 31–16 RES Reserved locations. Written as ZEROs and read as undefined. 15 PVALID EEPROM Valid status bit. ...
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PREAD command will terminate early, the PREAD bit will be cleared to a ZERO and the PVALID bit will remain reset with a value of ZERO. This applies to the automatic EEPROM after H_RESET as well as to host initiated ...
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AMD 12–5 RES Reserved locations. Written as ZERO, read as undefined. 4 EEN EEPROM port enable. When this bit is set to a one, it causes the values of ECS, ESK and EDI to be driven onto the EECS, EESK ...
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EDI/EDO EEPROM Data In / EEPROM Data Out. Data that is written to this bit will appear on the EEDI output of the Microwire interface, except when the PREAD bit is set to ONE or the EEN bit is ...
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AMD 7–0 SWSTYLE Software Style register. The value in this register determines the style of I/O resources that shall be used by the PCnet-PCI controller. The Software Style selection will affect the interpre- tation of a few bits within the ...
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Initialization Block When SSIZE32=0 (BCR20, bit 8), then the software structures are defined bits wide. The base ad- dress of the Initialization block in this mode must be aligned to a WORD boundary, i.e. CSR1, bit 0 ...
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AMD If a value other than those listed in the above table is de- sired, CSR76 and CSR78 can be written after initializa- tion is complete. See the description of the appropriate CSRs. When SSIZE32=1 (BCR20, bit 8), then the ...
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The Logical Address Filter is used in multicast address- ing schemes. The acceptance of the incoming frame based on the filter value indicates that the message may be intended for the node the node’s responsibility to determine if ...
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AMD RMD0 Bit Name Description 31–0 RBADR Receive Buffer address. This field contains the address of the receive buffer that is associated with this descriptor. RMD1 Bit Name Description 31 OWN This bit indicates that the de- scriptor entry is ...
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RMD2 Bit Name Description 31–24 RCC Receive Collision Count. Indi- cates the accumulated number of collisions on the network since the last packet was received, ex- cluding collisions that occurred during transmissions from this node. The PCnet-PCI implemen- tation of ...
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AMD Transmit Descriptors When SSIZE32=0 (BCR 20, bit 8), then the software structures are defined bits wide, and transmit descriptors look like this (CXDA = Current Transmit De- scriptor Address): Table 17. 16-Bit Data Structure Transmit Descriptor ...
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This function differs from the ILACC function for this bit. NO_FCS NO_FCS dynamically controls the generation of FCS on a frame by frame basis valid only if the ENP bit is set. When NO_FCS is set, the ...
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AMD before the end of the frame was reached. Upon UFLO error, the transmitter is turned off (CSR0, TXON = 0). UFLO is set by the PCnet-PCI cleared by the host. 29 EXDEF Excessive Deferral. Indicates that the transmitter has ...
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Register Summary PCI Configuration Registers Note read only read/write undefined value Offset Name 00h Vendor ID 02h Device ID 04h Command 06h Status 08h Revision ID 09h Programming IF 0Ah Sub-Class 0Bh Base-Class 0Dh ...
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AMD Control and Status Registers (continued) Default Value RAP Addr Symbol H_RESET 22 CSR22 uuuu uuuu 23 CSR23 uuuu uuuu 24 CSR24 uuuu uuuu 25 CSR25 uuuu uuuu 26 CSR26 uuuu uuuu 27 CSR27 uuuu uuuu 28 CSR28 uuuu uuuu ...
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Control and Status Registers (continued) Default Value RAP Addr Symbol H_RESET 65 CSR65 uuuu uuuu 66 CSR66 uuuu uuuu 67 CSR67 uuuu uuuu 68 CSR68 uuuu uuuu 69 CSR69 uuuu uuuu 70 CSR70 uuuu uuuu 71 CSR71 uuuu uuuu 72 ...
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AMD Control and Status Registers (continued) Default Value RAP Addr Symbol H_RESET 108 CSR108 uuuu uuuu 109 CSR109 uuuu uuuu 110 CSR110 uuuu uuuu 111 CSR111 uuuu uuuu 112 CSR112 uuuu 0000 113 CSR113 uuuu uuuu 114 CSR114 uuuu 0000 ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . Supply ...
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AMD DC CHARACTERISTICS (continued) Parameter Symbol Parameter Description VASQ DI and CI Differential Input Threshold (Squelch) VIRDVD DI and CI Differential Mode Input Voltage Range VICM DI and CI Input Bias Voltage VOPD DO Undershoot Voltage at ZERO Differential on ...
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DC CHARACTERISTICS (continued) Parameter Symbol Parameter Description Power Supply Current IDD Active Power Supply Current IDDCOMA Sleep Mode Power Supply Current IDDSNOOZE Auto Wake Mode Power Supply Current Pin Capacitance CIN Input Pin Capacitance CO I/O or Output Pin Capacitance ...
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AMD SWITCHING CHARACTERISTICS: Bus Interface Parameter Symbol Parameter Description Clock Timing CLK Frequency tCYC CLK Period tHIGH CLK High Time tLOW CLK Low Time tFALL CLK Fall Time tRISE CLK Rise Time Output and Float Delay Timing tVAL AD[31:00], C/BE[3:0], ...
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SWITCHING CHARACTERISTICS: 10BASE-T Interface Parameter Symbol Parameter Description Transmit Timing tTETD Transmit Start of Idle tTR Transmitter rise time tTF Transmitter fall time tTM Transmitter rise and fall time mismatch tPERLP Idle Signal Period tPWLP Idle Link Pulse Width tPWPLP ...
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AMD SWITCHING CHARACTERISTICS: Attachment Unit Interface Parameter Symbol Parameter Description AUI Port tDOTR DO+, DO– Rise Time (10% to 90%) tDOTF DO+, DO– Fall Time (10% to 90%) tDORM DO+, DO– Rise and Fall Time Mismatch tDOETD DO End of ...
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KEY TO SWITCHING WAVEFORMS SWITCHING TEST CIRCUITS Sense Point WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from H ...
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AMD SWITCHING TEST CIRCUITS DO+ DO– TXD+ TXD– Includes test jig capacitance TXP+ TXP– Includes test jig capacitance 1-1008 52.3 Test Point 154 100 ...
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SWITCHING WAVEFORMS: System Bus Interface CLK CLK AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL, IDSEL GNT HIGH 2.4V 2 LOW 1.5 V 0.8 V ...
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AMD SWITCHING WAVEFORMS: System Bus Interface CLK AD[31:00] C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL, PERR, SERR REQ CLK AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL AD[31:00], C/BE[3:0], PAR, FRAME, IRDY, TRDY, STOP, LOCK, DEVSEL 1-1010 P ...
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SWITCHING WAVEFORMS: 10BASE-T Interface TXD+ TXP+ TXD– TXP– t XMTON XMT (Note 1) Note: 1. Internal signal and is shown for clarification only. t PWPLP TXD+ TXP+ TXD– TXP– t PWLP ...
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AMD SWITCHING WAVEFORMS: 10BASE-T Interface RXD RXD 1-1012 Receive Thresholds (LRT=0) Receive Thresholds (LRT=1) Am79C970 V TSQ+ V THS+ V THS– V TSQ– tmau_RCV_LRT_HI 18220C-45 V LTSQ+ V LTHS+ ...
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SWITCHING WAVEFORMS: Attachment Unit Interface XTAL1 t XI ISTDCLK (Note 1) ITXEN (Note 1) 1 ITXDAT+ (Note 1) DO+ DO– DO Note: 1. Internal signal and is shown for clarification only. XTAL1 ISTDCLK (Note 1) ITXEN (Note ...
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AMD SWITCHING WAVEFORMS: Attachment Unit Interface XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ (Note 1) DO+ DO– Bit (n–2) Note: 1. Internal signal and is shown for clarification only. Transmit Timing – End of Frame ...
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SWITCHING WAVEFORMS: Attachment Unit Interface CI+/– V ASQ t PWOCI DO+/– PWKCI Collision Timing t DOETD 40 mV 100 mV max. 80 Bit Times Port DO ETD Waveform ...
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APPENDIX A PCnet-PCI Compatible Media Interface Modules PCnet-PCI Compatible 10BASE-T Filters and Transformers The table below provides a sample list of PCnet-PCI compatible 10BASE-T filter and transformer modules available from various vendors. Contact the respective manufacturer for a complete and ...
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PCnet-PCI Compatible AUI Isolation Transformers The table below provides a sample list of PCnet-PCI compatible AUI isolation transformers available from various vendors. Contact the respective manufacturer for a complete and updated listing of components. Manufacturer Bel Fuse A553-0506-AB Bel Fuse ...
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AMD MANUFACTURER CONTACT INFORMATION Contact the following companies for further informa- tion on their products. Company Bel Fuse Phone: FAX: Halo Electronics Phone: FAX: PCA Electronics Phone: (HPC in Hong Kong) FAX: Pulse Engineering Phone: FAX: Valor Electronics Phone: FAX: ...
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APPENDIX B Recommendation for Power and Ground Decoupling The mixed analog/digital circuitry in the PCnet-PCI make it imperative to provide noise-free power and ground connections to the device. Without clean power and ground connections, a design may suffer from high ...
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AMD VDD plane AVDD2 AVSS2 PCnet-PCI To determine the value for the resistor and capacitor, the formula is Where Ohms and microfarads. Some pos- sible ...
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APPENDIX C Alternative Method for Initialization The PCnet-PCI controller may be initialized by perform- ing I/O writes only. That is, data can be written directly to the appropriate control and status registers (CSR in- stead of reading from the initialization ...
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APPENDIX D Look-Ahead Packet Processing (LAPP) Concept Introduction of the LAPP Concept A driver for the PCnet-PCI controller would normally re- quire that the CPU copy receive frame data from the controllers buffer space to the applications buffer space after ...
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Outline of the LAPP Flow This section gives a suggested outline for a driver that utilizes the LAPP feature of the PCnet-PCI controller. Note: The labels in the following text are used as refer- ences in the timeline diagram that ...
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AMD C7: After filling the second buffer and performing the last chance lookahead to the next descriptor, the PCnet-PCI controller will write the status and change the ownership bit of descriptor number 2. S6: After the ownership of descriptor number ...
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Ethernet Wire Controller activity: C9: Controller writes descriptor #3. C8: Controller is performing intermittent N2: EOM bursts of DMA to fill data buffer #3. C7: Controller writes descriptor #2. C6: "Last chance" lookahead to descriptor #3 (OWN). C5: Controller is ...
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AMD tion call latency, minus the time needed for the driver to write to the third descriptor, minus the time needed for the driver to copy data from buffer #1 to the application buffer space, and minus the time needed ...
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The controller will discard all descriptors with OWN = 1 and STP = 0 and move to the next de- scriptor when searching for a place to begin a new frame. It discards these descriptors by simply changing the ownership ...
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AMD Note that the PCnet-PCI controller might write a ZERO to ENP location in the 3rd descriptor. Here are the two possibilities the controller finishes the data transfers into buffer number 2 after the driver writes the applica- ...
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An average increase in performance can be achieved if the general guidelines of buffer sizes in figure 2 is fol- lowed. However, as was noted earlier, the correct sizing for buffers will depend upon the expected message size. There are ...
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AMD Figure D3 shows the event flow for the two-interrupt method: Ethernet Wire Controller activity: } C10: ERP interrupt is generated. C9: Controller writes descriptor #3. C8: Controller is performing intermittent bursts of DMA to fill data buffer #3. N2: ...
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Figure D4 shows the buffer sizing for the two-interrupt method. Note that the second buffer size will be about the same for each method. Descriptor OWN = 1 #1 SIZE = HEADER_SIZE (minimum 64 bytes) Descriptor OWN = 1 #2 ...
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AMD DATA SHEET REVISION SUMMARY The following list represents the key differences be- tween revision B (May 1994) and revision C (June 1994). Global Change DWIO mode cannot be set by reading the EEPROM or writing directly to BCR18. The ...
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Page 1-982: BCR18—The descriptions for bits 5 and 6 are rewritten for clarity. Page 1-994: Tabel 18—The table is cleaned up for clarity. DC Characteristics Page 1-1001: VOL The maximum value is 0. IOL ...
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AMD 1-1034 Am79C970 ...
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