HY57V56420CT-H Hynix Semiconductor, HY57V56420CT-H Datasheet

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HY57V56420CT-H

Manufacturer Part Number
HY57V56420CT-H
Description
Manufacturer
Hynix Semiconductor
Datasheet
ORDERING INFORMATION
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.4 / July 2003
DESCRIPTION
The HY57V56420C is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large
memory density and high bandwidth. HY57V56420C is organized as 4banks of 16,777,216x4.
HY57V56420C is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized
with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage
levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or
write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3±0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by DQM
Internal four banks operation
HY57V56420CLT-K
HY57V56420CLT-H
HY57V56420CLT-P
HY57V56420CLT-S
HY57V56420CLT-6
HY57V56420CLT-8
HY57V56420CT-H
HY57V56420CT-6
HY57V56420CT-K
HY57V56420CT-8
HY57V56420CT-P
HY57V56420CT-S
Part No.
Clock Frequency
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
166MHz
133MHz
133MHz
125MHz
100MHz
100MHz
Low power
Power
Normal
4Banks x 16Mbits x 4
4 Banks x 16M x 4Bit Synchronous DRAM
Organization
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
Programmable CAS Latency ; 2, 3 Clocks
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Interface
LVTTL
HY57V56420C(L)T
400mil 54pin TSOP II
Package
1

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HY57V56420CT-H Summary of contents

Page 1

... Data mask function by DQM • Internal four banks operation ORDERING INFORMATION Part No. Clock Frequency HY57V56420CT-6 HY57V56420CT-K HY57V56420CT-H HY57V56420CT-8 HY57V56420CT-P HY57V56420CT-S HY57V56420CLT-6 HY57V56420CLT-K HY57V56420CLT-H HY57V56420CLT-8 HY57V56420CLT-P HY57V56420CLT-S This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described ...

Page 2

PIN CONFIGURATION PIN DESCRIPTION PIN PIN NAME CLK Clock CKE Clock Enable CS Chip Select BA0, BA1 Bank Address A0 ~ A12 Address Row Address Strobe, RAS, CAS, WE Column Address Strobe, Write Enable DQM Data Input/Output Mask DQ0 ~ ...

Page 3

FUNCTIONAL BLOCK DIAGRAM 16Mbit x 4banks x 4 I/O Synchronous DRAM Self refresh logic & timer CLK Row active CKE CS RAS CAS refresh WE Column Active DQM Bank Select A0 Address Registers A1 A12 BA0 BA1 Mode Registers Rev. ...

Page 4

ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature Storage Temperature Voltage on Any Pin relative Voltage on V relative Short Circuit Output Current Power Dissipation Soldering Temperature ⋅ Time Note : Operation at above absolute ...

Page 5

CAPACITANCE (TA=25 °C , f=1MHz) Parameter Input capacitance CLK A0 ~ A12, BA0, BA1, CKE, CS, RAS, CAS, WE, DQM Data input / output capacitance DQ0 ~ DQ3 OUTPUT LOAD CIRCUIT Output DC Output Load Circuit DC CHARACTERISTICS I Parameter ...

Page 6

... Self Refresh Current I DD6 Note : 1.I and I depend on output loading and cycle rates. Specified values are measured with the output open DD1 DD4 2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II 3.HY57V56420CT-6/K/H/8/P/S 4.HY57V56420CLT-6/K/H/8/P/S Rev. 0.4 / July 2003 ± (TA ° =3.3 0.3V, V =0V Test Condition ≥ ...

Page 7

AC CHARACTERISTICS I Parameter Symbol CAS Latency = 3 tCK3 System Clock Cycle Time CAS Latency = 2 tCK2 Clock High Pulse Width tCHW Clock Low Pulse Width tCLW CAS Latency = 3 tAC3 Access Time From Clock CAS Latency ...

Page 8

AC CHARACTERISTICS II Parameter Symbol Operation tRC RAS Cycle Time Auto Refresh tRRC RAS to CAS Delay tRCD RAS Active Time tRAS RAS Precharge Time tRP RAS to RAS Bank Active Delay tRRD CAS to CAS Delay tCCD Write Command ...

Page 9

IBIS SPECIFICATION I Characteristics (Pull-up) OH 100MHz 100MHz Voltage (Min) (Max) (V) I(mA) I(mA) 3.45 -2.4 3.3 -27.3 3.0 0 -74.1 2.6 -21.1 -129.2 2.4 -34.1 -153.3 2.0 -58.7 -197 1.8 -67.3 -226.2 1.65 -73 -248 1.5 -77.9 -269.7 1.4 ...

Page 10

DEVICE OPERATING OPTION TABLE HY57V56420C(L)T-6 CAS Latency 166MHz(6ns) 3CLKs 143MHz(7ns) 3CLKs 133MHz(7.5ns) 2CLKs HY57V56420C(L)T-K CAS Latency 133MHz(7.5ns) 2CLKs 125MHz(8ns) 3CLKs 100MHz(10ns) 2CLKs HY57V56420C(L)T-H CAS Latency 133MHz(7.5ns) 3CLKs 125MHz(8ns) 3CLKs 100MHz(10ns) 2CLKs HY57V56420C(L)T-8 CAS Latency 125MHz(8ns) 3CLKs 100MHz(10ns) 2CLKs 83MHz(12ns) 2CLKs ...

Page 11

COMMAND TRUTH TABLE Command CKEn-1 Mode Register Set No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Burst Stop DQM Auto Refresh Burst-Read-Single- WRITE Entry 1 Self Refresh Exit Entry Precharge ...

Page 12

PACKAGE INFORMATION 400mil 54pin Thin Small Outline Package 22.327(0.8790) 22.149(0.8720) 0.150(0.0059) 0.050(0.0020) 0.400(0.016) 0.80(0.0315)BSC 0.300(0.012) Rev. 0.4 / July 2003 UNIT : mm(inch) 11.938(0.4700) 11.735(0.4620) 10.262(0.4040) 10.058(0.3960) 5deg 0.597(0.0235) 0.210(0.0083) 0deg 0.120(0.0047) 0.406(0.0160) HY57V56420C(L)T 1.194(0.0470) 0.991(0.0390) 12 ...

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