HY5DU56822BT-D43 Hynix Semiconductor, HY5DU56822BT-D43 Datasheet
HY5DU56822BT-D43
Related parts for HY5DU56822BT-D43
HY5DU56822BT-D43 Summary of contents
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... DDR SDRAM HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Aug. 2003 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 ...
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... Changed VDDmin from 2.4V to 2.5V at Page22 2) Corrected some typos. 2. Revision 0.3 (Feb. 2003) 1) IDD value update at Page 23, 24. 2) Changed some AC Paramters on AC Characteristics Table at Page27, 28. 3. Revision 0.4 (Aug. 2003) 1) Corrected some contents of Power-Up Sequence and Device Initialization.(tXSNR,tXSRD) Rev. 0.4 / Aug. 2003 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 2 ...
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... DESCRIPTION The Hynix HY5DU56422BT ,HY5DU56822BT are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock ...
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... TSOP -II 17 0.65mm pin pitch ROW AND COLUMN ADDRESS TABLE ITEMS 64Mx4 16M 4banks A0 - A12 A0-A9, A11 BA0, BA1 A10 Refresh 8K HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 x8 x4 VSS 66 VSS DQ7 65 NC VSSQ 64 VSSQ DQ6 62 DQ3 VDDQ 61 VDDQ DQ5 59 NC VSSQ 58 VSSQ NC 57 ...
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... Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. Data input / output pin : Data bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection. HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 5 ...
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... Prefetch Unit 8 Bank 16Mx4 / Bank0 Control 16Mx4 / Bank1 16Mx4 / Bank2 16Mx4 / Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL CLK, DLL /CLK Block Mode Register HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 4 DQS DQ[0:3] DQS Data Strobe Transmitter Data Strobe DQS Receiver 6 ...
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... Prefetch Unit 16 Bank 8Mx8 / Bank0 Control 8Mx8 / Bank1 8Mx8 / Bank2 8Mx8 / Bank3 Mode Row Register Decoder Column Decoder Column Address Counter CLK_DLL CLK, DLL /CLK Block Mode Register HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 8 DQS DQ[0:7] DQS Data Strobe Transmitter Data Strobe DQS Receiver 7 ...
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... If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. Rev. 0.4 / Aug. 2003 CKEn CS RAS HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 A10/ CAS WE ADDR code code Note 1 1,4 X 1,5 ...
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... Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively. Rev. 0.4 / Aug. 2003 CKEn /CS, /RAS, /CAS, / HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 ADD A10 Note 1 ...
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... OPCODE BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Command Action DSEL NOP or power down NOP NOP or power down BST ILLEGAL ILLEGAL ILLEGAL ACT Row Activation PRE/PALL NOP AREF/SREF Auto Refresh or Self Refresh MRS Mode Register Set DSEL NOP NOP NOP BST ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Command Action ACT ILLEGAL PRE/PALL Term burst, precharge AREF/SREF ILLEGAL MRS ILLEGAL DSEL Continue burst to end NOP Continue burst to end BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ...
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... BA OPCODE BA, CA, AP READ/READAP HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Command Action DSEL NOP - Enter ROW ACT after tRCD NOP NOP - Enter ROW ACT after tRCD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter ROW ACT after tWR NOP ...
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... BA, CA, AP READ/READAP L L BA, CA, AP WRITE/WRITEAP OPCODE HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Command Action ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL AREF/SREF ILLEGAL MRS ILLEGAL DSEL NOP - Enter IDLE after tMRD NOP NOP - Enter IDLE after tMRD BST ILLEGAL ILLEGAL ILLEGAL ACT ILLEGAL PRE/PALL ILLEGAL ...
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... HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 /ADD Action X INVALID X Exit self refresh, enter idle after tSREX X Exit self refresh, enter idle after tSREX X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue self refresh X INVALID X Exit power down, enter idle X Exit power down, enter idle X ILLEGAL X ILLEGAL X ILLEGAL X NOP, continue power down mode ...
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... SREX PDEN PDEX AREF ACT POWER DOWN PDEN PDEX BANK ACTIVE WRITE READ WITH WITH AUTOPRE- AUTOPRE- CHARGE CHARGE WRITE PRE- CHARGE POWER-UP POWER APPLIED HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 SELF REFRESH AUTO REFRESH BST READ READAP READ WRITEAP PRE(PALL) Command Input Automatic Sequence 15 ...
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... DLL) 6. Issue Precharge commands for all banks of the device. Rev. 0.4 / Aug. 2003 Sequencing Voltage relationship to avoid latch-up After or with VDD After or with VDDQ After or with VDDQ HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V 16 ...
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... CODE CODE tRP tMRD tMRD EMRS Set MRS Set Precharge All Precharge All Reset DLL (with A8=H) * 200 cycle(tXSRD are required (for DLL locking) before Read Command HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 AREF MRS ACT CODE CODE CODE CODE CODE CODE tRP tRFC tMRD ...
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... Rev. 0.4 / Aug. 2003 CAS Latency A7 Test Mode No 0 Normal Yes 1 Test CAS Latency Reserved Reserved Reserved 1 2 Reserved HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Burst Length Burst Length Sequential Reserved Reserved Reserved Reserved Reserved A3 Burst Type 0 Sequential 1 Interleave Interleave Reserved Reserved ...
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... A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table Rev. 0.4 / Aug. 2003 Sequential XX0 0, 1 XX1 1, 0 X00 X01 X10 X11 000 001 010 011 100 101 110 111 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Interleave ...
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... Selection of the half strength driver option will reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver and the half strength driver are included in this document. Rev. 0.4 / Aug. 2003 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 20 ...
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... All bits in RFU address fields must be programmed to Zero, all reserved states not defined in this specification should not be used, as unknown operation or incompatibility with future versions may result. ** This part do not support /QFC function, A2 must be programmed to Zero. Rev. 0.4 / Aug. 2003 RFU* HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 0** DS DLL A0 DLL enable 0 Enable ...
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... DD of the transmitting device, and to track variations in the dc level of the same. DDQ (TA=0 to 70°C, Voltage referenced to V Symbol Min 0. =0V OUT HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Rating -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0 260 ⋅ 0V) SS Max Unit 2 0.3 V DDQ - V - 0.15 ...
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... DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min); All banks active CKE=<0.2V; External clock on; tCK=tCK(min) Four bank interleaving with BL=4, Refer to the following page for detailed test condition HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 = 0V) SS Speed -D4 -D43 130 130 ...
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... DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min); All banks active CKE=<0.2V; External clock on; tCK=tCK(min) Four bank interleaving with BL=4, Refer to the following page for detailed test condition HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 = 0V) SS Speed -D4 -D43 130 130 ...
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... DDR400(200Mhz, CL=3) : tCK = 5ns, CL=3, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read : RA0 A2 RA1 A3 RA2 N RA3 - repeat the same timing with random address changing 50% of data changing at every burst Legend : A=Activate, R=Read, RA=Read with Auto Precharge, W=Write, P=Precharge, N=NOP Rev. 0.4 / Aug. 2003 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 25 ...
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... Rev. 0.4 / Aug. 2003 o (TA Voltage referenced to V Symbol Min 0.31 IH(AC) REF V IL(AC) V 0.7 ID(AC) V 0.5*V IX(AC) DDQ o (TA Voltage referenced to VSS = 0V HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 = 0V) SS Max Unit 0.31 V REF V + 0.6 V DDQ -0.2 0.5*V +0.2 V DDQ Value Unit x 0.5 V DDQ x 0.5 V DDQ + 0.31 V REF - 0 ...
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... tCK 5 tCH 0.45 tCL 0.45 tAC -0.7 tDQSCK -0.55 tDQSQ - t HP tQH -t QHS min tHP (tCL,tCH) tQHS - tHZ tLZ -0.7 tIS 0.6 tIH 0 0.7 IH HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 DDR400 (D43) Unit Max Min Max - 70K 40 70K ns tRCD tRASmin - ...
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... DSH 1.75 - 1.75 DIPW t 0.9 1.1 RPRE t 0.4 0.6 RPST WPRES t 0.25 - 0.25 WPREH t 0.4 0.6 WPST MRD t 200 - 200 XSRD tXSNR 7.8 REFI HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Unit Note Max 2 1.28 CK 0.2 CK 0 6,7,11, 12,13 0 0.9 1.1 CK 0.4 0 0.4 0 ...
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... Slew Rate2=0.4V/n then the Delta Inverse Slew Rate=-0.5ns/V. (1/SlewRate1)-(1/SlewRate2) ns/V 0 +/-0.25 +/- 0.5 Rev. 0.4 / Aug. 2003 Delta tIS Delta tIH +50 0 +100 0 Delta tDS Delta tDH +75 +75 +150 +150 Delta tDS Delta tDH ps ps +50 +50 Delta tDS Delta tDH +50 +50 +100 +100 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 29 ...
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... These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). Rev. 0.4 / Aug. 2003 HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 30 ...
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... Rev. 0.4 / Aug. 2003 Pin CK, /CK, CKE CK, /CK All other input-only pins All other input-only pins DQ, DQS, DM DQ, DQS VDDQ/2, V peak-to-peak = 0. =50 Ω Zo=50 Ω V REF C =30pF L HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Symbol Min Max C 2.0 3.0 I1 Delta 2.0 3.0 I1 Delta 4.0 5.0 IO ...
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... Rev. 0.4 / Aug. 2003 BASE PLANE 22.33 (0.879) 22.12 (0.871) 0.35 (0.0138) 0.25 (0.0098) SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) HY5DU56422BT-D4/D43 HY5DU56822BT-D4/D43 Unit : mm(Inch) 11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396 Deg. 0.597 (0.0235) 0.210 (0.0083) 0.406 (0.0160) 0.120 (0.0047) ...