THC63LVD103 Integrated Device Technology, Inc., THC63LVD103 Datasheet

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THC63LVD103

Manufacturer Part Number
THC63LVD103
Description
Manufacturer
Integrated Device Technology, Inc.
Datasheet

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V103 Datasheet
General Description
The V103 LVDS display interface transmitter is
primarily designed to support pixel data transmission
between a video processing engine and a digital video
display. The data rate supports up to SXGA+
resolutions and can be used in Plasma, Rear Projector,
Front Projector, CRT and LCD display applications. It
can also be used in other high-bandwidth parallel data
applications and provides a low EMI interconnect over
a low cost, low bus width cable up to several meters in
length.
The V103 converts 35 bits of CMOS/TTL data, clocked
on the rising or falling edge of an input clock
(selectable), into six LVDS (Low Voltage Differential
Signaling) serial data stream pairs. In video
applications the 35 bits is normally divided into 10 bits
for each R, G and B channel and 5 control bits.
When combined with the V104 LVDS display interface
receiver, the V103 + V104 combination provides a
35-bit wide, 90 MHz transport. The rate of each LVDS
channel is 630 Mbps for a 90MHz data input clock, 945
Mbps for 135MHz.
Block Diagram
I n t e g r a t e d C i r c u i t S y s t e m s • 5 2 5 R a c e St r e e t , S a n J o s e , C A 9 5 1 2 6 • t e l ( 4 0 8) 2 97 - 1 2 0 1 • w ww. i c s t . co m
V103
T
RIPLE
(8 to 135 MHz)
10-B
/PWDN
CLKIN
TC0-6
TD0-6
TA0-6
TB0-6
TE0-6
R/F
IT
RS
LVDS T
7
7
7
7
7
to Serial
Parallel
1
RANSMITTER FOR
PLL
Features
Pin compatible with THine THC63LVD103
Wide pixel clock range: 8 - 135 MHz
Supports a wide range of video and graphics modes
including VGA, SVGA, XGA, SXGA, SXGA+, NTSC,
PAL, SDTV, and HDTV up to 1080I or 720P
Internal PLL requires no external loop filter
Selectable rising or falling clock edge for data
alignment
Compatible with Spread Spectrum clock source
Reduced LVDS output voltage swing mode
(selectable) to minimize EMI
CMOS/TTL data inputs can be configured for
reduced input voltage swing
Single 3.3 V supply
Low power consumption CMOS design
Power down mode
64-pin TQFP lead free package
TA+
TC-
TD-
TCLK-
TA-
TB-
TE+
TC+
TD+
TE-
TCLK+
TB+
V
IDEO
11/23/06
Revision 2.0

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THC63LVD103 Summary of contents

Page 1

... • • • LVDS T IT RANSMITTER FOR Features • Pin compatible with THine THC63LVD103 • Wide pixel clock range 135 MHz • Supports a wide range of video and graphics modes including VGA, SVGA, XGA, SXGA, SXGA+, NTSC, PAL, SDTV, and HDTV up to 1080I or 720P • ...

Page 2

V103 T 10-B LVDS T RIPLE IT Pin Assignment TD5 1 GND 2 TD6 3 TE0 4 TE1 5 TE2 6 7 VCC TE3 8 TE4 9 10 GND 11 TE5 CLKIN 12 /PWDN 13 14 PLLGND PLLVCC 15 TE6 ...

Page 3

V103 T 10-B LVDS T RIPLE IT Pin Descriptions Pin Pin Pin Type Number Name 30, 31 TA+, TA- 28, 29 TB+, TB- 24, 25 TC+, TC- LVDS OUT 20, 21 TD+, TD- 18, 19 TE+, TE- 22, 23 TCLK+, ...

Page 4

V103 T 10-B LVDS T RIPLE IT External Components Decoupling capacitors should be used for all power pins. The V103 requires no other external components. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ...

Page 5

V103 T 10-B LVDS T RIPLE IT DC Electrical Characteristics VDD=3.3 V ±10%, Ambient temperature 0 to +70 ° C Parameter CMOS/TTL Inputs, Standard Configuration Input High Voltage Input Low Voltage Input Current CMOS/TTL Inputs, Small Input Swing Configuration Max ...

Page 6

V103 T 10-B LVDS T RIPLE IT Gray Scale Pattern CLKIN Worst Case Pattern CLKIN Tx0 Tx1 Tx2 Tx3 ...

Page 7

V103 T 10-B LVDS T RIPLE IT VDD=3.3 V ±10%, Ambient temperature 0 to +70 ° C Parameter Symbol Switching Characteristics CLK IN Transition Time CLK IN Period CLK IN High Time CLK IN Low Time CLK IN to TCLK± ...

Page 8

V103 T 10-B LVDS T RIPLE IT AC Timing Diagrams TTL Input LVDS Output V DIFF TTL Inputs CLK IN Tx0-Tx6 TCLK+ V103 Datasheet ...

Page 9

V103 T 10-B LVDS T RIPLE IT Small Swing Inputs Tx0-Tx6 LVDS Output V DIFF TCLK OUT (Differential) TA+/- TB+/- TC+/- TD+/- TE+/- Previous Cycle t 1 TOP t 0 TOP V103 Datasheet ...

Page 10

V103 T 10-B LVDS T RIPLE IT Phase Lock Loop Set Time /PWDN VCC CLKIN TCLKx+/- V103 Datasheet ...

Page 11

V103 T 10-B LVDS T RIPLE IT Package Outline and Package Dimensions Package dimensions are kept current with JEDEC Publication No. 95, variation ACD. ALL DIMENSIONS ARE IN MILLIMETERS. Ordering Information Part / Order Number Marking V103YLF V103YLF V103YLFT V103YLF ...

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