CY62126VL-70ZC Cypress Semiconductor Corporation., CY62126VL-70ZC Datasheet

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CY62126VL-70ZC

Manufacturer Part Number
CY62126VL-70ZC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY62126VL-70ZC

Case
TSSOP-44L

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Part Number
Manufacturer
Quantity
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Part Number:
CY62126VL-70ZC
Manufacturer:
CY
Quantity:
12
Features
Functional Description
The CY62126V is a high-performance CMOS static RAM or-
ganized as 65,536 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption by 99% when deselected. The device enters
power-down mode when CE is HIGH.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
Cypress Semiconductor Corporation
• 2.7V–3.6V operation
• CMOS for optimum speed/power
• Low active power (70 ns)
• Low standby power (70 ns, LL version)
• Automatic power-down when deselected
• Independent control of Upper and Lower Bytes
• Available in 44-pin TSOP II (forward)
A
A
A
Logic Block Diagram
A
A
A
A
A
A
A
12
11
10
— 198 mW (max.) (55 mA)
— 54 W (max.) (15 A)
1
0
9
7
6
3
2
COLUMN DECODER
DATA IN DRIVERS
1024 X 1024
RAM Array
64K x 16
3901 North First Street
PRELIMINARY
I/O
I/O
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
I/O pins (I/O
fied on the address pins (A
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O
data from memory will appear on I/O
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY62126V is available in standard 44-pin TSOP Type II
(forward pinout) and mini-BGA packages.
1
9
– I/O
– I/O
BHE
WE
CE
OE
BLE
62126V–1
8
16
15
). If byte high enable (BHE) is LOW, then data from
San Jose
9
1
through I/O
to I/O
64K x 16 Static RAM
8
. If byte high enable (BHE) is LOW, then
Pin Configurations
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
V
WE
A
A
A
A
NC
CE
CC
A
A
A
A
A
SS
16
15
14
13
12
TSOP II (Forward)
4
3
2
1
0
1
2
3
4
5
6
7
8
0
1
) is written into the location speci-
through A
CA 95134
through I/O
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
10
11
12
Top View
9
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
15
to I/O
).
62126V–2
16
A
A
A
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
NC
A
A
A
A
NC
CY62126V
February 13, 1998
) are placed in a
1
5
6
7
SS
CC
8
9
10
11
16
16
15
14
13
12
11
10
9
through I/O
. See the truth
408-943-2600
8
), is
0

Related parts for CY62126VL-70ZC

CY62126VL-70ZC Summary of contents

Page 1

Features • 2.7V–3.6V operation • CMOS for optimum speed/power • Low active power (70 ns) — 198 mW (max.) (55 mA) • Low standby power (70 ns, LL version) — (max.) (15 A) • Automatic power-down when deselected ...

Page 2

Pin Configurations (continued) Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Shaded areas contain advance information. Maximum Ratings (Above which the useful life may be impaired. For user guide- lines, not tested.) Storage Temperature ................................. –65 ...

Page 3

Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH [1] V Input LOW Voltage IL I Input Load Current IX I Output Leakage Current OZ I ...

Page 4

Switching Characteristics Over the Operating Range Parameter READ CYCLE t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data ...

Page 5

Data Retention Characteristics Parameter Description V V for Data Retention Data Retention Current CCDR [4] t Chip Deselect to Data Retention Time CDR t Operation Recovery Time R Data Retention Waveform Switching Waveforms [10,11] ...

Page 6

Switching Waveforms (continued) [13,14] Write Cycle No. 1 (CE Controlled) ADDRESS CE t BHE, BLE WE DATA I/O Write Cycle No. 2 (WE Controlled, OE HIGH During Write) ADDRESS BHE, BLE OE t HZOE DATA I/O ...

Page 7

Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW) ADDRESS BHE, BLE t HZWE NOTE 15 DATAI/O Truth Table BLE BHE High ...

Page 8

... Ordering Information Speed (ns) Ordering Code 55 CY62126V-55ZC CY62126VL-55ZC CY62126VLL-55ZC CY62126VLL-55ZI 55 CY62126V-55BAC CY62126VL-55BAC CY62126VLL-55BAC CY62126VLL-55BAI 70 CY62126V-70ZC CY62126VL-70ZC CY62126VLL-70ZC CY62126VLL-70ZI 70 CY62126V-70BAC CY62126VL-70BAC CY62126VLL-70BAC CY62126VLL-70BAI Shaded area contains advanced information. Document #: 38–00584 Package Diagrams PRELIMINARY Package Name Package Type Z44 44-Lead TSOP II Z44 44-Lead TSOP II ...

Page 9

Package Diagrams (continued) 48-Ball (7. 7.00 mm) Mini Ball Grid Array BA48 © Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any ...

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