CY62127DV18LL-55BVI Cypress Semiconductor Corporation., CY62127DV18LL-55BVI Datasheet

CY62127DV18LL-55BVI

Manufacturer Part Number

CY62127DV18LL-55BVI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY62127DV18LL-55BVI.pdf (13 pages)

Specifications of CY62127DV18LL-55BVI

Case

BGA-48D

Current page: 1 of 13
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Cypress Semiconductor Corporation

Document #:

Features

Functional Description

The CY62127DV18 is a high-performance CMOS static RAM

organized as 64K words by 16 bits. This device

vanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life

applications such as cellular telephones.

an automatic power-down feature that significantly reduces

power consumption by

The device can be put into standby mode reducing power con-

sumption by more than 99% when deselected

(CE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

• Very

•

• Ultra-low active power

• Ultra-low standby power

• Easy memory expansion with

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Packages offered in a 48-ball FBGA and a 44-pin TSOP

Voltage range: 1.65V to 1.95V

Type II

— Typical active current:

Logic Block Diagram

) HIGH or Chip Enable 2 (CE

high speed:

38-05226

55 ns

99%

Rev.

when addresses are not toggling.

[1]

0.5

2.5

Power-down

Circuit

COLUMN DECODER

mA @ f = 1 MHz

mA @ f = f

DATA IN DRIVERS

) LOW

2048 x 32 x 16

, CE

RAM ARRAY

64K × 16

(MoBL

The device

•

or both BHE

and OE features

MAX

3901 North First Street

Chip Enable 1

features ad-

) in portable

also has

and

INFORMATION

ADVANCE

BLE are HIGH. The input/output pins

placed in a high-impedance state when: deselected

able 1 (CE

disabled (OE HIGH),

Enable are disabled

ation

HIGH and WE LOW).

Writing to the device is accomplished by taking Chip Enable 1

(CE

(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O

specified on the

Enable (BHE) is LOW, then data from I/O pins (I/O

I/O

Reading from the device is accomplished by taking Chip En-

able 1 (CE

Enable (OE) LOW while forcing the Write Enable (WE) HIGH.

If Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins will appear on I/O

I/O

ory will appear on I/O

of this data sheet for a complete description of read and write

modes.

BHE

BLE

through A

. If Byte High Enable (BHE) is LOW, then data from mem-

) LOW and Chip Enable 2 (CE

) is written into the location specified on the address pins

(Chip Enable 1 (CE

•

1M (64K

San Jose

) LOW and Chip Enable 2 (CE

) HIGH or Chip Enable 2 (CE

I/O

address pins (A

–I/O

through I/O

(BHE, BLE HIGH) or during a write oper-

BHE

BLE

both Byte High Enable and Byte Low

to I/O

•

) LOW and Chip Enable 2 (CE

x 16) Static RAM

CA 95134

. See the truth table at the back

Revised September 24, 2002

), is written into the location

through A

CY62127DV18

) HIGH and Write Enable

(I/O

) LOW, outputs are

•

) HIGH and Output

through I/O

408-943-2600

MoBL2

). If Byte High

Chip En-

through

) are

)

Related parts for CY62127DV18LL-55BVI

CY62127DV18LL-55BVI Summary of contents

Page 1

Features • Very high speed • Voltage range: 1.65V to 1.95V • Ultra-low active power — Typical active current: 0 MHz — Typical active current: 2 • Ultra-low ...

Page 2

Pin Configuration TSOP II (Forward) Top View BHE ...

... V Range(V) CC Product Min. Typ. CY62127DV18L 1.65 1.8 CY62127DV18LL Notes: 3. VIL(min.) = -2.0V for pulse durations less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ 25°C. Document #: 38-05226 Rev. ** ADVANCE INFORMATION DC Input Voltage Output Current into Outputs (LOW) ...

Page 4

DC Electrical Characteristics Parameter Description V Output HIGH Voltage OH V Output LOW Voltage OL V Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage Current IX I Output Leakage Current Operating Supply Cur- ...

Page 5

AC Test Loads and Waveforms INCLUDING JIG AND SCOPE Equivalent to: OUTPUT Parameters Data Retention Characteristics Parameter Description V V for ...

Page 6

Switching Characteristics (Over the Operating Range) Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW or CE ACE LOW to ...

Page 7

Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) ADDRESS ATA OUT PREVIOUS DATA VALID [14, 15] Read Cycle No. 2 (OE Controlled) ADDRESS BHE HIGH ...

Page 8

Switching Waveforms (continued) Write Cycle No. 1 (WE Controlled) ADDRESS E ATA I/O DON’ T CARE t HZOE Write Cycle No. 2 (CE1 or CE Controlled) 2 ADDRESS ...

Page 9

Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS DATA I/O DON’ T CARE t HZWE Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) ADDRESS BHE/ ...

Page 10

... Ordering Information Speed (ns) Ordering Code 55 CY62127DV18L-55BVI CY62127DV18LL-55BVI CY62127DV18L-55ZI CY62127DV18LL-55ZI Document #: 38-05226 Rev. ** ADVANCE INFORMATION BLE Input / Outputs X X High High High Data Out ( I/O0 – I/O15 Data Out ( I/O0 – I/O7); High Z (I/O8 – I/O15 High Z (I/O0 – I/O7); Data Out ( I/O8 – I/O15) ...

Page 11

Package Diagrams Document #: 38-05226 Rev. ** ADVANCE INFORMATION 48-ball VFBGA ( mm) BV48A CY62127DV18 ® MoBL2 51-85150-*A Page ...

Page 12

MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05226 Rev. ** © Cypress Semiconductor ...

Page 13

Document History Page Document Title: CY62127DV18 MoBL2 Document Number: 38-05226 Issue REV. ECN NO. Date ** 118006 10/01/02 Document #: 38-05226 Rev. ** ADVANCE INFORMATION ® 1M (64K x 16) Static RAM Orig. of Change Description of Change CDY New ...

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