CY7C09199-12AC Cypress Semiconductor Corporation., CY7C09199-12AC Datasheet
CY7C09199-12AC
Specifications of CY7C09199-12AC
Related parts for CY7C09199-12AC
CY7C09199-12AC Summary of contents
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Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Six Flow-Through/Pipelined devices — 64K x 8/9 organizations (CY7C09089/189) — 128K x 8/9 organizations (CY7C09099/199) • Three Modes — Flow-Through — Pipelined ...
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Functional Description The CY7C09089/99 and CY7C09189/99 are high-speed syn- chronous CMOS 64K and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. isters on control, address, ...
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Pin Configurations 100 A7L 3 A8L 4 A9L 5 A10L 6 A11L 7 A12L 8 A13L 9 A14L 10 A15L 11 [5] A16L 12 VCC ...
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... SB1 (Both ports TTL Level) Typical Standby Current for I (mA) SB3 (Both ports CMOS Level) Note: 7. This pin is NC for CY7C09189. Document #: 38-06039 Rev. *A 100-Pin TQFP (Top View CY7C09199 (128K x 9) CY7C09189 (64K CY7C09089/99 CY7C09089/99 CY7C09189/99 CY7C09189/99 [ 100 83 6.5 7.5 ...
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... Outputs in High Z State ................................. –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Note: 8. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 9. Industrial parts are available in CY7C09099 and CY7C09199 only. Document #: 38-06039 Rev. *A Description A for 64K; and A A for 128K devices). ...
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Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage Min –4.0 mA Output LOW Voltage Min +4.0 mA Input HIGH Voltage ...
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AC Test Loads 893 OUTPUT 347 (a) Normal Load (Load 1) AC Test Loads (Applicable to -6 only OUTPUT 1.4V TH ...
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Switching Characteristics Over the Operating Range Parameter Description f f Flow-Through MAX1 Max f f Pipelined MAX2 Max t Clock Cycle Time - Flow-Through CYC1 t Clock Cycle Time - Pipelined CYC2 t Clock HIGH Time - Flow-Through CH1 t ...
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Switching Waveforms Read Cycle for Flow-Through Output (FT/PIPE = V t CYC1 t CH1 CLK R ADDRESS t CD1 DATA OUT t ...
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Switching Waveforms (continued) [18, 19] Bank Select Pipelined Read t CYC2 t t CH2 CL2 CLK ADDRESS A (B1 0(B1) DATA OUT(B1 ADDRESS A (B2) ...
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Switching Waveforms (continued) Pipelined Read-to-Write-to-Read ( CYC2 t t CH2 CL2 CLK R ADDRESS DATA IN DATA OUT ...
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Switching Waveforms (continued) Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK R ADDRESS DATA IN t CD1 ...
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Switching Waveforms (continued) Pipelined Read with Address Counter Advance t CYC2 t t CH2 CL2 CLK ADDRESS SAD HAD ADS CNTEN t t SCN HCN DATA OUT ...
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Switching Waveforms (continued) Write with Address Counter Advance (Flow-Through or Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS n INTERNAL A n ADDRESS t t SAD HAD ADS CNTEN t t SCN HCN ...
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Switching Waveforms (continued) [17, 24, 30, 31] Counter Reset (Pipelined Outputs) t CYC2 t t CH2 CL2 CLK ADDRESS INTERNAL A X ADDRESS SAD HAD ADS t t SCN HCN CNTEN t t SRST HRST ...
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Read/Write and Enable Operation Inputs OE CLK Address Counter Control Operation Previous Address Address CLK ADS CNTEN ...
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... Synchronous Dual-Port SRAM Speed (ns) Ordering Code 6.5 CY7C09199-6AC 7.5 CY7C09199-7AC 9 CY7C09199-9AC CY7C09199-9AI 12 CY7C09199-12AC Document #: 38-06039 Rev. *A Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack ...
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Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06039 Rev. *A © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of ...
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Document Title: CY7C09089/99, CY7C09189/99 64K/128K x 8/9 Synchronous Dual Port Static RAM Document Number: 38-06039 Issue REV. ECN NO. Date Change ** 110187 10/21/01 *A 122289 12/27/02 Document #: 38-06039 Rev. *A Orig. of Description of Change SZV Change from ...