CY7C09349A-9AC Cypress Semiconductor Corporation., CY7C09349A-9AC Datasheet
CY7C09349A-9AC
Specifications of CY7C09349A-9AC
Related parts for CY7C09349A-9AC
CY7C09349A-9AC Summary of contents
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... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • Two Flow-Through/Pipelined devices — organization (CY7C09349A) — organization (CY7C09359A) • Three Modes — Flow-Through — Pipelined — Burst • Pipelined output mode on both ports allows fast 100-MHz cycle time • ...
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... Functional Description The CY7C09349A and CY7C09359A are high-speed synchro- nous CMOS 4K and dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory. control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time ...
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... Max. Access Time (ns) (Clock to Data, Pipelined) Typical Operating Current I (mA) CC Typical Standby Current for I (mA) SB1 (Both Ports TTL Level) Typical Standby Current for I (mA) SB3 (Both Ports CMOS Level) Note: 4. This pin is NC for CY7C09349A. Document #: 38-06048 Rev. *A 100-Pin TQFP (Top View CY7C09359A (8K x 18) ...
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... For read operations both Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage............................................ >2001V Latch-Up Current..................................................... >200 mA Operating Range Range Commercial [6] Industrial 6. Industrial Parts are available in CY7C09359A only. CY7C09349A CY7C09359A AND CE must be asserted MAX –I/O ). 8/9L 15/17L Ambient Temperature V ...
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... Test Conditions MHz 5.0V CC AND CE must be asserted to their active states ( CY7C09349A CY7C09359A -9 -12 Unit 2.4 2.4 V 0.4 0.4 V 2.2 2.2 V 0.8 0.8 V –10 10 – 215 360 195 300 mA 240 ...
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... Test Conditions pF. Document #: 38-06048 Rev 250 TH OUTPUT 1.4V TH (b) Thévenin Equivalent (Load 1) [8] 3.0V 10% GND Capacitance (pF) (b) Load Derating Curve CY7C09349A CY7C09359A 893 OUTPUT 347 (c) Three-State Delay (Load 2) (Used for & t CKLZ OLZ OHZ including scope and jig) ALL INPUT PULSES 90% 90% 10 ...
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... CWDD t Clock to Clock Set-up Time CCS Note: 9. Test conditions used are Load 2. Document #: 38-06048 Rev. *A CY7C09349A CY7C09359A [ Min. Max. Min. Max. Min. Max 100 6.5 7.5 12 6 6.5 7 CY7C09349A CY7C09359A -12 Min. Max. Unit 33 MHz 50 MHz Page [+] Feedback ...
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... n+1 t OHZ [10, 11, 12, 13 CL2 A A n+1 n+2 t CD2 CKLZ = following the next rising edge of the clock constantly loads the address on the rising edge of the CLK. Numbers are for reference only. IL CY7C09349A CY7C09359A n+3 t CKHZ Q n OLZ n n+1 n+2 t OHZ t OLZ ...
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... Document #: 38-06048 Rev CD2 HC CD2 SC CKHZ CKLZ [16, 17, 18, 19] NO MATCH t CD1 NO MATCH t CWDD VALID . for the left port, which is being written to. IH CY7C09349A CY7C09359A CD2 CKHZ CKLZ CD2 CKHZ CD2 CKLZ t CD1 VALID >maximum specified, then data is not CWDD CCS Page [+] Feedback ...
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... During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity. Document #: 38-06048 Rev. *A [13, 20, 21, 22 n+1 n CD2 CKHZ OPERATION [13, 20, 21, 22 n+1 n+2 n n+2 n+3 t CD2 OHZ WRITE . IH CY7C09349A CY7C09359A A A n+3 n CD2 CKLZ Q n+3 WRITE READ A A n+4 n CKLZ CD2 Q n+4 READ Page [+] Feedback ...
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... DATA OUT OE Document #: 38-06048 Rev. *A [11, 13, 20, 21 n+1 n+2 n n+2 t CD1 Q n+1 t CKHZ NO READ OPERATION [11, 13, 20, 21 n+1 n+2 n n+2 n OHZ READ WRITE CY7C09349A CY7C09359A n+3 n CD1 CD1 Q n CKLZ WRITE READ A A n+4 n CD1 t CD1 Q n CKLZ DC READ Page [+] Feedback ...
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... IL 1 Document #: 38-06048 Rev. *A [23] t SAD t SCN t CD2 n+1 COUNTER HOLD READ WITH COUNTER [23 n+1 COUNTER HOLD READ WITH COUNTER . IH CY7C09349A CY7C09359A t HAD t HCN Q Q n+2 n+3 READ WITH COUNTER t t SAD HAD t t SCN HCN Q Q n+2 n+3 READ WITH ...
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... The “Internal Address” is equal to the “External Address” when ADS = V Document #: 38-06048 Rev. *A [24, 25 n+1 n+1 n+2 WRITE WITH WRITE COUNTER COUNTER HOLD . IH and equals the counter output when ADS = V IL CY7C09349A CY7C09359A n+2 n+3 n n+3 n+4 WRITE WITH COUNTER . IH Page [+] Feedback ...
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... SD DATA DATA OUT COUNTER RESET Notes: 26 UB, and 27. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. Document #: 38-06048 Rev WRITE READ ADDRESS 0 ADDRESS 0 ADDRESS 1 CY7C09349A CY7C09359A n n READ READ ADDRESS n Page [+] Feedback ...
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... CNTRST I/O Mode Reset out( Load out( Hold out( Increment out(n+ CY7C09349A CY7C09359A Operation [31] Deselected [31] Deselected Write [31] Read Outputs Disabled Operation Counter Reset to Address 0 Address Load into Counter External Address Blocked—Counter Disabled Counter Enabled—Internal Address Generation Page [+] Feedback ...
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... Ordering Information 4K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09349A-6AC 7.5 CY7C09349A-7AC 9 CY7C09349A-9AC 12 CY7C09349A-12AC 8K x18 Synchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 6.5 CY7C09359A-6AC 7.5 CY7C09359A-7AC 9 CY7C09359A-9AC CY7C09359A-9AI 12 CY7C09359A-12AC Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 Document #: 38-06048 Rev. *A © ...
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... Document Title: CY7C09349A/CY7C09359A 4K/ Synchronous Dual-Port Static RAM Document Number: 38-06048 Issue Orig. of REV. ECN NO. Date Change ** 110200 09/29/01 SZV *A 122298 12/27/02 RBI Document #: 38-06048 Rev. *A Description of Change Change from Spec number: 38-00834 to 38-06048 Power up requirements added to Maximum Ratings Information CY7C09349A CY7C09359A ...