CY7C4841-15AI Cypress Semiconductor Corporation., CY7C4841-15AI Datasheet
CY7C4841-15AI
Available stocks
Related parts for CY7C4841-15AI
CY7C4841-15AI Summary of contents
Page 1
... Double 256 x 9 (CY7C4801) • Double 512 x 9 (CY7C4811) • Double (CY7C4821) • Double (CY7C4831) • Double (CY7C4841) • Double (CY7C4851) • Functionally equivalent to two CY7C4201/4211/4221/ 4231/4241/4251 FIFOs in a single package • 0.65 micron CMOS for optimum speed/power • ...
Page 2
... CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 39 10 CY7C4851 RSA CY7C4801/4811/4821 CY7C4831/4841/4851 LDA LDB EFA PAEA PAFA FFA EFB PAEB PAFB ...
Page 3
... T is the “instant on” case temperature. A CY7C4801/4811/4821 CY7C4831/4841/4851 7C48X1-25 7C48X1- CY7C4841 CY7C4851 Double Double 64-pin TQFP 64-pin TQFP [1] Ambient Temperature + 10 + 10% Page [+] Feedback ...
Page 4
Pin Definitions Signal Name Description I/O DA Data Inputs Data Inputs Data Outputs Data Outputs Write Enable 1 I WENA1 WENB1 Write Enable 2 I ...
Page 5
Electrical Characteristics Over the Operating Range Parameter Description V Output HIGH Voltage Output LOW Voltage Input HIGH Voltage IH V Input LOW Voltage IL I Input Leakage V ...
Page 6
Switching Characteristics Over the Operating Range Parameter Description f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock HIGH Time CLKH t Clock LOW Time CLKL t Data Set-Up Time DS t Data ...
Page 7
Switching Waveforms Write Cycle Timing WCLKA (WCLKB ( WENA1 (WENB1) WENA2(WENB2) (if applicable) FFA (FFB) t SKEW1 RCLKA (RCLKB) RENA1,RENB2 (RENB1, RENB2) Read Cycle Timing RCLKA (RCLKB ENS ENH RENA1,RENA2 ...
Page 8
Switching Waveforms (continued) [13] Reset Timing RSA(RSB) RENA1, RENA2 (RENB1,RENB2) WENA1 (WENB1) WENA2/LDA [15] (WENB2/LDB) EFA, PAEA (EFB, PAEB) FFA, PAFA (FFB, PAFB ( Notes: 13. The clocks (RCLKA,RCLKB, WCLKA,WCLKB) can be ...
Page 9
Switching Waveforms (continued) First Data Word Latency after Reset with Simultaneous Read and Write WCLKA,WCLKB (FIRSTVALID WRITE ( ENS WENA1(WENB1) WENA2(WENB2) (if applicable) t SKEW1 RCLKA(RCLKB) EFA(EFB) ...
Page 10
Switching Waveforms (continued) Empty Flag Timing WCLKA,WCLKB t DS DATA WRITE1 ( ENH ENS WENA1(WENB1 ENS ENH WENA2(WENB2) [16] (if applicable) t FRL RCLKA(RCLKB) t SKEW1 EFA(EFB) RENA1, ...
Page 11
Switching Waveforms (continued) Full Flag Timing NO WRITE WCLKA,WCLKB [11] t SKEW1 ( WFF FFA(FFB) WENA1(WENB1) WENA2(WENB2) (if applicable) RCLKA(RCLKB) t ENH t ENS RENA1, RENA2 (RENB1,RENB2) LOW OEA(OEB ...
Page 12
... If a write is performed on this rising edge of the write clock, there will be Full - (m-1) words of the FIFO when (PAFA,PAFB) goes LOW. 22. (PAFA,PAFB) offset = m. 23. 256-m words in FIFO for CY7C4801, 512-m words for CY7C4811, 1024-m words for CY7C4821, 2048-m words for CY7C4831, 4096-m words for CY7C4841, 8192-m words for CY7C4851. ...
Page 13
Switching Waveforms (continued) Write Programmable Registers t CLK t CLKH WCLKA,WCLKB t ENS WENA2/LDA (WENB2/LDB) t ENS WENA1(WENB1 ( PAE OFFSET Read Programmable Registers t CLK t CLKH RCLKA(RCLKB) t ...
Page 14
Architecture The CY7C48X1 functions as two independent FIFOs in a single package, each with its own separate set of controls. The device con- sists of two arrays of 256 to 8K words of 9 bits each (imple- mented by a ...
Page 15
... LOW when the number of unread words in the FIFO is greater than or equal to CY7C4801 (256–m), CY7C4811 (512–m), CY7C4821 (1K–m), CY7C4831 (2K–m), CY7C4841 (4K–m), and CY7C4851 (8K–m). (PAFA,PAFB) is set HIGH by the LOW-to-HIGH transition of (WCLKA,WCLKB) when the number of available memory locations is greater than m ...
Page 16
... CY7C4801 0 0 [26] [26 (n+1) to (256-(m+1)) (n+1) to (512-(m+1)) [27] (256 m) to 255 (512 m) 256 512 Number of Words in FIFO CY7C4831 CY7C4841 0 0 [26] [26 (n+1) to (2048 (m+1)) (n+1) to (4096 (m+1)) (n+1) to (8192 (m+1)) [27] [27] (2048 m) to 2047 (4096 m) to 4095 2048 4096 Notes: 26. n =Empty Offset (n=7 default value). ...
Page 17
... RESET (RSA,RSB) ( DATA OUT READ CLOCK (RCLKA,RCLKB) CY7C4801 READ ENABLE 1 (RENA1,RENB1) CY7C4811 CY7C4821 CY7C4831 OUTPUT ENABLE (OEA,OEB) CY7C4841 CY7C4851 PROGRAMMABLE(PAEA,PAEA) EMPTY FLAG(EFA,EFB) Read Enable 2 (RENA2,RENB2) Used in a Single Device Configuration. CY7C4801/4811/4821 CY7C4831/4841/4851 QA ( 48X1– ...
Page 18
Width Expansion Configuration Word width may be increased simply by connecting the corre- sponding input control signals of FIFOs A and B. A composite flag should be created for each of the end-point status flags EFA and EFB, also FFA ...
Page 19
... RENA2 CC WENA2 RCLKA WCLKA OEA WENA1 9 RENA1 CY7C4801 CY7C4811 CY7C4821 CY7C4831 CY7C4841 CY7C4851 RAM ARRAY B WENB1 RCLKB RENB1 WCLKB OEB WENB2 RENB2 V CC data. a typical application would have the expansion logic al- ternate data access from one device to the next in a sequential manner ...
Page 20
Ordering Information Double 256x9 FIFO Speed Package (ns) Ordering Code Name 10 CY7C4801-10AC A65 CY7C4801-10AI A65 15 CY7C4801-15AC A65 CY7C4801-15AI A65 25 CY7C4801-25AC A65 CY7C4801-25AI A65 35 CY7C4801-35AC A65 CY7C4801-35AI A65 Double 512x9 FIFO Speed Package (ns) Ordering Code Name ...
Page 21
... CY7C4831-25AI A65 35 CY7C4831-35AC A65 CY7C4831-35AI A65 Double 4Kx9 FIFO Speed Package (ns) Ordering Code Name 10 CY7C4841-10AC A65 CY7C4841-10AI A65 15 CY7C4841-15AC A65 CY7C4841-15AI A65 25 CY7C4841-25AC A65 CY7C4841-25AI A65 35 CY7C4841-35AC A65 CY7C4841-35AI A65 Double 8Kx9 FIFO Speed Package (ns) Ordering Code Name 10 CY7C4851-10AC A65 CY7C4851-10AI ...
Page 22
Package Diagram Document #: 38-06005 Rev. *A © Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a ...
Page 23
Document Title: CY7C4801/4811/4821/CY7C4831.4841/4851 256/512/1K/2K/4K/ Double Sync (TM) Fifos Document Number: 38-06005 Issue Orig. of REV. ECN NO. Date Change ** 106466 07/11/01 *A 122258 12/26/02 Document #: 38-06005 Rev. *A Description of Change SZV Change from Spec Number: ...