AD1895 Analog Devices, AD1895 Datasheet
AD1895
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AD1895 Summary of contents
Page 1
... MCLK internally to reduce noise and EMI emissions on the board. When MCLK is synchronous to either the output or input serial port, the AD1895 can be configured in a master mode where MCLK is divided down and used to generate the left/right and bit clocks for the serial port that is synchronous to MCLK. ...
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... AD1895–SPECIFICATIONS TEST CONDITIONS, UNLESS OTHERWISE NOTED. Supply Voltages VDD_CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 V VDD_IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.3 V Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30.0 MHz Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 1.000 kHz, 0 dBFS Measurement Bandwidth . . . . . . . . . . . . . . . . . . Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bits Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 pF Input Voltage High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 V Input Voltage Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 V DIGITAL PERFORMANCE (VDD_CORE = 3.3 V ...
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... A t SIH t SIL t SOH t SOL t DOH –3– 10%) Min Max 33 30 200 MCLK IN RESET t RSTL Figure 2. RESET Timing t MPWH t MPWL Figure 3. MCLK_IN Timing AD1895 Unit ns MHz ...
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... AD1895 –SPECIFICATIONS DIGITAL FILTERS (VDD_CORE = 3.3 V Parameter Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Specifications subject to change without notice. DIGITAL I/O CHARACTERISTICS (VDD_CORE = 3.3 V Parameter Input Voltage High ( Input Voltage Low ( Input Leakage ( Input Leakage (I ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1895 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Master/Slave Clock Ratio Mode Select Pin 0 Master/Slave Clock Ratio Mode Select Pin 1 Master/Slave Clock Ratio Mode Select Pin 2 PIN CONFIGURATION NC 1 MMODE_2 28 MCLK_IN 2 MMODE_1 27 MCLK_OUT 3 26 MMODE_0 AD1895 SDATA_I 4 25 SCLK_O TOP VIEW SCLK_I 5 24 LRCLK_O ) (NOT TO SCALE LRCLK_I 6 SDATA_O 23 VDD_IO ...
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... FREQUENCY – kHz TPC 3. Wideband FFT Plot (16 k Points) 48 kHz: 96 kHz, 0 dBFS 1 kHz Tone REV. B Typical Performance Characteristics–AD1895 –100 –120 –140 –160 –180 –200 15.0 17.5 20.0 22.5 TPC 4. Wideband FFT Plot (16 k Points) 44.1 kHz: 192 kHz, 0 dBFS 1 kHz Tone – ...
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... AD1895 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 0 2.5 5.0 7.5 10.0 12.5 FREQUENCY – kHz TPC 7. Wideband FFT Plot (16 k Points) 192 kHz: 48 kHz, 0 dBFS 1 kHz Tone –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 – ...
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... TPC 17. IMD, 10 kHz and 11 kHz, 0 dBFS Tone, 48 kHz: 44.1 kHz –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 15.0 17.5 20.0 22.5 TPC 18. Wideband FFT Plot (16 k Points) 44.1 kHz: 48 kHz, 0 dBFS 20 kHz Tone –9– AD1895 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 FREQUENCY – kHz 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 FREQUENCY – kHz ...
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... AD1895 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 FREQUENCY – kHz TPC 19. Wideband FFT Plot (16 k Points) 192 kHz: 192 kHz, 0 dBFS 80 kHz Tone 0 –20 –40 –60 –80 –100 –120 –140 –160 –180 –200 0 2.5 5.0 7.5 10.0 12.5 15.0 FREQUENCY – kHz TPC 20 ...
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... TPC 30. DNR (Unweighted) vs. Output Sample Rate kHz, S_IN kHz, –60 dBFS 1 kHz Tone S_IN –11– AD1895 66000 102000 138000 174000 48000 84000 120000 156000 192000 OUTPUT SAMPLE RATE – kHz, S_IN 66000 ...
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... AD1895 –119 –121 –123 –125 –127 –129 –131 –133 –135 30000 66000 102000 48000 84000 120000 OUTPUT SAMPLE RATE – Hz TPC 31. DNR (Unweighted) vs. Output Sample Rate kHz, –60 dBFS 1 kHz Tone S_IN 0 –20 192kHz: 96kHz –40 –60 192kHz: 48kHz –80 192kHz: 32kHz – ...
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... TPC 42. Linearity Error, 192 kHz: 44.1 kHz, 0 dBFS to –140 dBFS Input, 200 Hz Tone –13– AD1895 –120 –100 –80 –60 –40 –20 INPUT LEVEL – dBFS –120 –100 –80 –60 –40 –20 INPUT LEVEL – dBFS – ...
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... AD1895 –110.0 –112.5 –115.0 –117.5 –120.0 –122.5 –125.0 –127.5 –130.0 –132.5 –135.0 –137.5 –140.0 –140 –120 –100 –80 –60 INPUT LEVEL – dBFS TPC 43. THD + N vs. Input Amplitude, 48 kHz: 44.1 kHz, 1 kHz Tone –110.0 –112.5 –115.0 –117.5 –120.0 –122.5 –125.0 –127.5 –130.0 – ...
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... The AD1895 input tolerant part and is available in a 28-lead SSOP SMD package. The AD1895 input tolerant only when the VDD_IO supply pin is supplied with 5 V. ...
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... This significantly reduces the resampling error. will be repeated S_IN can never be S_OUT . The AD1895 is S_IN 20 . OUT f = 1/T2 S_OUT Figure 5. Time Domain of the Interpolation and Resampling In the frequency domain shown in Figure 6, the interpolation expands the frequency axis of the zero-order hold ...
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... Since there are 2 with a 64-tap FIR filter, there needs cients for each tap, which requires a total of 2 reduce the number of coefficients in ROM, the AD1895 stores a small subset of coefficients and performs a high order interpola- tion between the stored coefficients. So far, the above approach works for the case of f > ...
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... AD1895 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –200 –210 –220 0.01 0.1 Figure 8. Frequency Response of the Digital Servo Loop. f frequency is 30 MHz. The digital servo loop is essentially a ramp filter that provides the initial pointer to the address in RAM and ROM for the start of the FIR convolution ...
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... It is recommended that the AD1895 be reset when changing modes. Power Supply and Voltage Reference The AD1895 is designed for 3 V operation with 5 V input toler- ance on the input pins. VDD_CORE is the 3 V supply that is used to power the core logic of the AD1895 and to drive the output pins ...
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... Table III. When the output word width is less than 24 bits, dither is added to the truncated bits. The Right-Justified Serial Data Out Mode assumes 64 SCLK_O cycles per frame, divided evenly 2 S, and right for left and right. The AD1895 also supports 16-bit, 32-clock packed input and output serial data in LJ, RJ, and I SMODE_OUT_[0: ...
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... Figure 12. Daisy-Chain Configuration for TDM Mode (First AD1895 Being Clock-Master) SHARC is a registered trademark of Analog Devices, Inc. REV the next AD1895, a large shift register is created and is clocked by SCLK_O. ® DSP. The The number of AD1895s that can be daisy-chained together is limited by the maximum frequency of SCLK_O, which is about 25 MHz. For example, if the output sample rate eight AD1895s could be connected since 512 × ...
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... AD1895 Serial Data Port Master Clock Modes Either of the AD1895 serial ports can be configured as a master serial data port. However, only one serial port can be a master, while the other has slave. In Master Mode, the AD1895 requires a 256 × 768 × f ...
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... PIN 1 2.00 MAX 0.05 MIN REV. B OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9. 5.60 8.20 5.30 7.80 5.00 7. 1.85 1.75 0.10 1.65 COPLANARITY 0.25 0.09 0.65 0.38 BSC 0.22 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-150AH –23– AD1895 8 0.95 4 0.75 0 0.55 ...
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... AD1895 Revision History Location 9/02—Data Sheet changed from REV REV. B. Changes to SPECIFICATIONS (Digital Performance Changes to SPECIFICATIONS (Digital Timing Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Replaced TPCs 1– Additions to RESET and Power-Down section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Changes to Figures 9a and .19 Additions to Serial Data Ports––Data Format section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 – ...