K4S161622E-TC70 Samsung, K4S161622E-TC70 Datasheet
K4S161622E-TC70
Specifications of K4S161622E-TC70
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K4S161622E-TC70 Summary of contents
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... K4S161622E SDRAM 512K x 16bit x 2 Banks Synchronous DRAM Samsung Electronics reserves the right to change products or specification without notice. LVTTL Revision 1.1 Jan 2003 CMOS SDRAM Rev 1.1 Jan '03 ...
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... ORDERING INFORMATION Part NO. K4S161622E-TC55 K4S161622E-TC60 K4S161622E-TC70 K4S161622E-TC80 K4S161622E-TC10 Data Input Register 512K x 16 512K x 16 Column Decoder Latency & Burst Length ...
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... K4S161622E PIN CONFIGURATION (TOP VIEW) A10/AP PIN FUNCTION DESCRIPTION Pin Name CLK System Clock CS Chip Select CKE Clock Enable /AP Address Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable L(U)DQM Data Input/Output Mask DQ ~ Data Input/Output ...
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... K4S161622E ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. ...
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... Self Refresh Current I CC6 Note : 1. Unless otherwise notes, Input level is CMOS(V 2. Measured with outputs open. Addresses are changed only one time during tcc(min). 3. Refresh period is 32ms. Addresses are changed only one time during tcc(min). 4. K4S161622E-TC Test Condition Latency Burst Length =1 t ...
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... K4S161622E AC OPERATING TEST CONDITIONS Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200 Output 50pF 870 (Fig Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) ...
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... K4S161622E Symbol Parameter CLK cycle time t CC(min) Row active to row active delay t RRD(min) RAS to CAS delay t RCD(min) Row precharge time t RP(min) Row active time t RAS(min) t RAS(max) Row cycle time Minimum delay is required to complete write. 3. All parts allow every cycle column address change. ...
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... K4S161622E SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address Auto Precharge Enable ...
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... K4S161622E MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS BA A /AP A Address 10 Function RFU RFU W.B.L Test Mode A A Type Mode Register Set 0 1 Reserved 1 0 Reserved 1 1 Reserved Write Burst Length Length Burst 1 Single Bit POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= " ...
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... K4S161622E BURST SEQUENCE (BURST LENGTH = 4) Initial Address BURST SEQUENCE (BURST LENGTH = 8) Initial Address ...
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... K4S161622E DEVICE OPERATIONS CLOCK (CLK) The clock input is used as the reference for all SDRAM opera- tions. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between V and V . During operation with CKE high all inputs are ...
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... K4S161622E DEVICE OPERATIONS (Continued) MODE REGISTER SET (MRS) The mode register stores the data for controlling the various operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The ...
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... K4S161622E DEVICE OPERATIONS (Continued) DQM OPERATION The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle ...
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... K4S161622E BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 1) Clock Suspended During Write (BL=4) CLK ...
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... K4S161622E 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD ADD DQ(CL2 DQ(CL3) tCCD Note 2 2) Write interrupted by Write (BL=2) CLK CMD WR WR tCCD Note ADD tCDL Note 3 *Note : 1. By " Interrupt" meant to stop burst read/write by external command before the end of burst. ...
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... K4S161622E 4. CAS Interrupt (II) : Read Interrupted by Write & DQM (a) CL=2, BL=4 CLK i) CMD RD DQM DQ ii) CMD RD DQM DQ iii) CMD RD DQM DQ iv) CMD RD DQM DQ (b) CL=3, BL=4 CLK i) CMD RD DQM DQ ii) CMD RD DQM DQ RD iii) CMD DQM DQ RD iii) CMD DQM DQ RD iv) CMD DQM DQ *Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. ...
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... K4S161622E 5. Write Interrupted by Precharge & DQM CLK WR CMD DQM *Note : 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only the other bank precharge of dual banks operation. ...
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... K4S161622E 6. Precharge 1) Normal Write (BL=4) CLK WR CMD Normal Read (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 7. Auto Precharge 1) Normal Write (BL=4) CLK WR CMD Normal Read (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) *Note : Last data in to row precharge delay RDL 2. Number of valid output data after row precharge : for CAS Latency = respectively. ...
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... K4S161622E 8. Burst Stop & Interrupted by Precharge 1) Normal Write (BL=4) CLK WR CMD DQM Read Interrupted by Precharge (BL=4) CLK CMD RD DQ(CL2) DQ(CL3) 9. MRS 1) Mode Register Set CLK Note 4 CMD PRE tRP *Note : CLK RDL CLK ; Last data in to burst stop delay. ...
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... K4S161622E 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit CLK CKE Internal Note 1 CLK ...
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... K4S161622E 12. About Burst Type Control Sequential Counting Basic MODE Interleave Counting Random Random column Access MODE CLK CCD 13. About Burst Length Control 1 2 Basic MODE 4 8 Full Page Special BRSW MODE Random Burst Stop MODE RAS Interrupt (Interrupted by Precharge) Interrupt ...
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... K4S161622E FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State IDLE Row Active Read ...
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... K4S161622E FUNCTION TRUTH TABLE (TABLE 1) Current CS RAS CAS State Row Activating Refreshing Mode Register Accessing Abbreviations : RA = Row Address NOP = No Operation Command *Note : 1 ...
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... K4S161622E FUNCTION TRUTH TABLE (TABLE 2) Current CKE CKE CS n State (n- Self Refresh All Banks Precharge Power Down All ...
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... K4S161622E Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 tCH CLOCK tCL tCC CKE *Note 1 CS tRCD tSH ...
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... K4S161622E *Note : 1. All inputs expect CKE & DQM can be don 2. Bank active & read/write are controlled by BA Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/ A10/AP and BA control bank precharge when precharge command is asserted. ...
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... K4S161622E Power Up Sequence CLOCK CKE High level is necessary CS tRP ...
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... K4S161622E Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS tRCD ...
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... K4S161622E Page Read & Write Cycle at Same Bank @Burst Length CLOCK CKE CS tRCD ...
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... K4S161622E Page Read Cycle at Different Bank @Burst Length CLOCK CKE *Note ...
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... K4S161622E Page Write Cycle at Different Bank @Burst Length CLOCK CKE ...
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... K4S161622E Read & Write Cycle at Different Bank @Burst Length CLOCK CKE ...
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... K4S161622E Read & Write Cycle with Auto Precharge I @Burst Length CLOCK CKE ...
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... K4S161622E Read & Write Cycle with Auto Precharge II @Burst Length CLOCK CKE ...
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... K4S161622E Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length CLOCK CKE ...
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... K4S161622E Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page CLOCK CKE ...
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... K4S161622E Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page CLOCK CKE ...
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... K4S161622E Burst Read Single bit Write Cycle @Burst Length CLOCK *Note 1 CKE ...
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... K4S161622E Active/Precharge Power Down Mode @CAS Latency=2, Burst Length ...
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... K4S161622E Self Refresh Entry & Exit Cycle ...
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... K4S161622E Mode Register Set Cycle CLOCK HIGH CKE CS *Note ...
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... K4S161622E PACKAGE DIMENSIONS 50-TSOP2-400CF #50 #1 20.95 0.10MAX [ ] 0.075MAX +0.10 (0.875) 0.30 -0.05 #26 #25 0.10 1.20MAX 0.80TYP +0.10 [0.80 0.08] 0.05MIN 0.35 -0.05 CMOS SDRAM Unit : Millimeters 0~8 0.25 TYP +0.075 0.125 -0.035 1.00 0.10 Rev 1.1 Jan '03 ...