K4S161622H-TC60 Samsung, K4S161622H-TC60 Datasheet
K4S161622H-TC60
Specifications of K4S161622H-TC60
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K4S161622H-TC60 Summary of contents
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... SDRAM 16Mb H-die(x16) 16Mb H-die SDRAM Specification Samsung Electronics reserves the right to change products or specification without notice. Revision 1.5 August 2004 CMOS SDRAM Rev. 1.5 August 2004 ...
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SDRAM 16Mb H-die(x16) Revision History Revision 0.0 (May, 2003) - Target spec release. Revision 0.1 (October, 2003) - Modified tRDL from 1CLK to 2CLK. Revision 0.2 (October, 2003) - Deleted AC parameter notes 5. Revision 0.3 (October, 2003) - Modified ...
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... O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable laten- cies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ORDERING INFORMATION Part NO. K4S161622H-TC55 K4S161622H-TC60 K4S161622H-TC70 K4S161622H-TC80 Organization 1Mx16 MAX Freq. ...
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SDRAM 16Mb H-die(x16) Package Physical Dimension #50 #1 0.10MAX [ ] 0.075MAX (0.875) #26 #25 20.95 r0.10 0.80TYP +0.10 +0.10 [0.80r0.08] 0.30 0.35 -0.05 -0.05 50Pin TSOP(II) Package Dimension CMOS SDRAM 0~8q 0.25 TYP +0.075 0.125 -0.035 1.20MAX 1.00 r0.10 ...
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... FUNCTIONAL BLOCK DIAGRAM Bank Select CLK ADD LCKE LRAS LCBR CLK CKE * Samsung Electronics reserves the right to change products or specification without notice. Data Input Register 512K x 16 512K x 16 Column Decoder Latency & Burst Length Programming Register LWE LCAS Timing Register ...
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SDRAM 16Mb H-die(x16) PIN CONFIGURATION (TOP VIEW) A10/AP PIN FUNCTION DESCRIPTION Pin Name CLK System Clock CS Chip Select CKE Clock Enable /AP Address Bank Select Address RAS Row Address Strobe CAS Column Address ...
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SDRAM 16Mb H-die(x16) ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on V supply relative to Vss DD Storage temperature Power dissipation Short circuit current Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS ...
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... Self Refresh Current I CC6 Note : 1. Unless otherwise notes, Input level is CMOS(V 2. Measured with outputs open. Addresses are changed only one time during tcc(min). 3. Refresh period is 32ms. Addresses are changed only one time during tcc(min). 4. K4S161622H- 70qC ) A Test Condition Burst Length =1 t (min) ...
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SDRAM 16Mb H-die(x16) AC OPERATING TEST CONDITIONS Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 3.3V 1200: Output 30pF 870: (Fig Output Load Circuit ...
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... Assumed input rise and fall time (tr & tf)=1ns & longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP Symbol ...
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SDRAM 16Mb H-die(x16) SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address ...